With the swift advancement of artificial intelligence and high-performance computing applications, there has been a significant uptick in market demand for memory solutions that offer both high capacity and high bandwidth. Nevertheless, high-speed SRAM, limited by its 6T cell structure, faces challenges in achieving substantial capacity. On the other hand, off-chip DRAM, characterized by relatively high access latency, falls short of meeting the stringent high-bandwidth demands. In this context, the IGZO-based 2T0C architecture emerges as a promising candidate. Its compatibility with back-end integration onto logic chips positions it as an optimal solution that harmonizes high capacity with high bandwidth. However, current research on 2T0C DRAM is primarily confined to planar and vertical 4F² architectures, lacking a streamlined, single-step approach for multi-layer 3D integration. This limitation hinders further enhancements in memory density.