On June 17th, Suanmiao Technology made an exciting announcement: its 3D TokenPU chip, the A4E, which is specifically tailored for large-scale model inference, officially completed tape-out on June 15th. Constructed upon a self-developed RISC-V architecture, incorporating proprietary IP, and supported by a self-built software ecosystem, this chip showcases an innovative design with an 8-layer memory wafer and compute logic wafer stacked vertically. By employing through-silicon via (TSV) and bump technology, it achieves micrometer-scale interconnections, dramatically reducing the traditional millimeter-scale transmission distance between chips by two orders of magnitude. This breakthrough leads to an ultra-high memory bandwidth of 16TB/s, effectively addressing the data bottleneck issues encountered in large-scale model inference. At present, Suanmiao Technology has successfully established a comprehensive domestic supply chain system that encompasses all aspects of chip development, including design, core IP, manufacturing, and packaging.