Today, He Tingbo, a member of Huawei's board of directors and president of its Semiconductor Business Department, has released a signed paper titled "A Time Scaling Theory for Multi-Layer Electronic Systems" on the pre-publication platform for scientific and technological papers hosted by the Chinese Academy of Sciences. The paper offers an in-depth exploration of the "Tao (τ) Law," which adopts "time" as the primary metric for technological advancement, rather than transistor area. It introduces a unified optimization objective centered around a single characteristic time constant, τ, applicable across the entire computing spectrum, from transistors to data centers.

Furthermore, the paper unveils a portion of Huawei's strategic roadmap for its Kirin and Ascend chip series. It projects that the efficiency of Kirin chip SoCs will more than double within the next 3 to 5 years. By 2035, the integration level of AI hardware is expected to surge by over 100 times. The CPU performance core frequency is set to reach 3.1GHz this year and surpass 4GHz by 2029. Regarding Ascend AI chips, the Ascend 910C and Ascend 950 are slated for launch between 2025 and 2026. Following this, the Ascend 990 will incorporate Chiplet, 2.5D fan-out, and 3D stacking technologies, introduce logical folding by 2030, and attain a more than 100-fold increase in hardware integration by 2035.

Additionally, the paper showcases two verification cases at the mass-production level. One case involves a mobile SoC that achieves a 55% increase in transistor density and a 41% improvement in energy efficiency through the application of logical folding technology. The other case presents an AI system that, by leveraging a unified memory-semantic bus, near-package optics Hi-ONE, and 3D folding technology, is anticipated to achieve a more than 100-fold increase in hardware integration by 2035.