Recently, the team at the Intelligent Computer Research Center, operating under the National Key Laboratory of Processor Chips, has achieved notable advancements in wafer-scale chip design and multi-chiplet fully homomorphic encryption accelerators. The trio of papers, namely [Paper Title 1], [Paper Title 2], and [Paper Title 3], delve into distinct yet interconnected topics: performance-convergence frameworks tailored for wafer-scale chips, pipelined parallel acceleration architectures specifically designed for multi-chiplet fully homomorphic encryption, and the automation of hardware framework design.

These research accomplishments have garnered recognition from prestigious international conferences, with acceptance at CGO 2026, NeurIPS 2025, and AAAI 2026. The laboratory, which enjoys the support of the Institute of Computing Technology at the Chinese Academy of Sciences and is steered by three academicians, is dedicated to tackling three pivotal challenges in processor chip development during the post-Moore era: the deceleration of process scaling, the exponential growth of design space, and the fragmentation of application ecosystems. Its research portfolio encompasses cutting-edge technologies such as open cross-layer optimization EDA and open-source intelligent design platforms.

To date, the laboratory has been honored with six national-level science and technology awards. Moreover, it has played a pivotal role in nurturing domestic processor enterprises like Loongson and Cambricon, which collectively boast a market capitalization surpassing 100 billion yuan.