Recently, the National Key Laboratory of Processor Chips at the Institute of Computing Technology, Chinese Academy of Sciences, has achieved notable advancements in architectural innovation for Fully Homomorphic Encryption (FHE) chips. Two of its research papers, titled [Please insert the actual titles of the papers here], have been accepted by DAC 2025, a premier conference in the field of Electronic Design Automation.

Hypnos tackles the challenges of low memory utilization and high communication overhead in FHE applications by introducing an innovative heterogeneous hardware acceleration architecture. Through a synergistic software-hardware co-design approach, it substantially enhances memory utilization, diminishes PCIe communication volume and associated overhead, and boosts end-to-end performance.

Ares, on the other hand, centers on FHE-based Private Set Intersection protocols and unveils the first hardware-software co-designed near-storage accelerator. By refining relinearization operations and implementing task decoupling strategies, it markedly improves hardware utilization and performance, while also reducing the energy efficiency ratio.

Since its inception in 1964, the DAC conference has consistently been at the forefront of innovation and development in the global Electronic Design Automation arena, earning it the reputation as the 'barometer of the chip design industry'.