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Lixin Semiconductor: Managing Leakage Power in the Back-End Design of 5nm and 2nm Chips
14 hour ago /
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Author：小编
As semiconductor technology progresses to the cutting-edge nodes of 5nm, 3nm, and even 2nm, the back-end design of chips encounters significant technical hurdles. In the 5nm process, transistor density soars to 130-150 million transistors per square millimeter (MTr/mm²), with the typical threshold voltage plummeting to 0.65V. Consequently, static power consumption can constitute as much as 45% of the total power. Although the 12nm process is now well-established, controlling leakage remains paramount. This is because leakage current escalates exponentially at elevated temperatures, thereby compromising chip performance and reliability. Similar challenges are prevalent across other advanced process nodes as well.
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