In the realm of semiconductor memory technology, Dynamic Random-Access Memory (DRAM) stands as a pivotal component within computing systems. However, enhancing density while simultaneously reducing power consumption has consistently posed as formidable challenges. With the advent of artificial intelligence and the proliferation of big data, traditional memory architectures are now struggling to keep pace with the escalating demands of data processing. In the prevalent 1T1C (one-transistor, one-capacitor) architecture, the relentless pursuit of process scaling has rendered it increasingly difficult to further miniaturize storage capacitors. Moreover, issues such as capacitor leakage and interference have intensified, posing significant obstacles. The 2T0C (two-transistor, zero-capacitor) architecture emerges as a promising alternative, yet traditional integration methodologies, which rely on a sequential stacking process, encounter hurdles such as lateral alignment discrepancies and the adverse effects of thermal cycling.