The ongoing evolution towards 5.5G/6G wireless communication, along with the push for next-generation serial interfaces to achieve higher transmission rates, has set stringent standards for the jitter performance of millimeter-wave local oscillator clocks. While sub-sampling phase-locked loops (PLLs) have emerged as the preferred choice for low-jitter clock chips, thanks to their high phase detection gain, traditional architectures are not without their flaws. Issues such as charge sharing effects, which compromise loop phase margin, the necessity for additional dummy sampling paths that drive up power consumption, and the degradation of oscillator phase noise due to the low quality factors of capacitors and varactors in the millimeter-wave band, pose significant challenges.

To overcome these hurdles, the Institute of Microelectronics at the Chinese Academy of Sciences, in collaboration with Tsinghua University, has introduced a groundbreaking dual-edge ping-pong sub-sampling PLL architecture. This innovative design leverages both the rising and falling edges of the reference clock to achieve equivalent frequency multiplication of the reference signal. By doing so, it effectively resolves the intricate trade-offs between loop bandwidth, in-band phase noise, and reference spurious design. Furthermore, the team has incorporated a highly power- and area-efficient injection-locked buffer scheme to minimize out-of-band phase noise.

Utilizing these cutting-edge technologies, a K-band PLL clock chip has been successfully designed using a 65nm CMOS process. This chip boasts an impressive output frequency range spanning from 22.4GHz to 25.6GHz, with an overall power consumption of less than 18mW. Its RMS integrated jitter performance is superior to 50fs, and it achieves a jitter-power consumption figure of merit of below −254dB, setting a new benchmark in the field.