Recently, Pan Quan's research team hailing from the National Demonstrative Microelectronics College, which is part of the College of Engineering at the Southern University of Science and Technology, has achieved remarkable advancements in the realm of high - speed communication and optoelectronic integrated circuit design. Their research has yielded results in the form of two chips.

The first chip is a linear modulator transmitter chip that seamlessly integrates inherent feedforward equalization and a breakdown voltage tripler. This chip adopts a half - rate linear transmitter architecture. It monolithically combines a 2 - to - 1 analog multiplexer and a linear driver. Through the precise timing relationship between the clock signal and the half - rate data stream, it realizes inherent feedforward equalization. Moreover, it employs a breakdown voltage tripler topology that utilizes stacked heterojunction bipolar transistors. This enables it to triple the output swing compared to traditional cascode structures while still ensuring reliability.

The second chip is a single - ended receiver front - end chip that supports multi - order crosstalk cancellation and signal reuse. In high - density channels, single - ended links are prone to far - end crosstalk. To tackle this issue, this chip introduces multi - order crosstalk cancellation and signal reuse technologies. By presenting an Nth - order far - end crosstalk model and adopting a second - order crosstalk cancellation topology, it significantly improves the horizontal and vertical eye opening. Specifically, under 112 Gb/s PAM - 4 signals, it enhances the horizontal eye opening by 24% and the vertical eye opening by 18%, achieving an optimal energy efficiency of 0.34 pJ/b.

Relevant research papers have been published in the IEEE Journal of Solid - State Circuits (JSSC).