Samsung Releases Performance Metrics for Its Initial 2nm Chip Batch, Stepping Up Competition with TSMC
2025-11-19 / Read about 0 minute
Author:小编   

On November 19, Samsung Electronics disclosed the inaugural batch of performance metrics for its forthcoming 2nm chip manufacturing process. This move signals Samsung's intensified push in next-generation wafer foundry production, aiming to close the gap with industry leader TSMC. Samsung revealed that its first-generation 2nm process leverages Gate-All-Around (GAA) transistor technology, resulting in a 5% performance boost, an 8% enhancement in power efficiency, and a 5% reduction in chip area when compared to its second-generation 3nm process. This announcement marks Samsung's maiden release of detailed specifications for 2nm chips, transitioning from prior conceptual overviews. Presently, TSMC commands over 70% of the global wafer foundry market, whereas Samsung holds roughly 7%. The majority of analysts anticipate TSMC to maintain its dominant position, attributed to its high production output, consistent manufacturing, and escalating demand for AI accelerators and data center chips. Nevertheless, South Korean industry experts predict that competition could heat up significantly at the 2nm node.