TSMC is ramping up the development of its cutting-edge 2-nanometer chip manufacturing process. The company has confirmed that its N2 process will commence mass production prior to the end of 2025. Simultaneously, TSMC is expanding its production facilities both in Taiwan and in Arizona, USA.

The N2 node leverages a Gate-All-Around (GAA) transistor architecture. This advanced design offers a significant performance boost, with improvements ranging from 10% to 15%, and a substantial reduction in power consumption, estimated between 25% and 30%, when compared to the 3nm process.

Among the initial customers for this technology are industry giants such as Apple, AMD, and Nvidia. The foundry price for the 2-nanometer process is set at around $30,000 per wafer.

In Taiwan, the monthly production capacity at the Baoshan and Kaohsiung plants is projected to reach between 45,000 and 50,000 wafers by the end of 2025. This capacity is expected to more than double, surpassing 100,000 wafers by 2026. Meanwhile, the Fab21 campus in Arizona is also advancing its N2 process layout. Notably, the originally planned introduction of the N3 node in 2028 has been expedited. Furthermore, an optimized N2P process is slated for launch in the latter half of 2026.