Recently, a team of researchers from the Institute of Microelectronics at the Chinese Academy of Sciences has made a significant breakthrough. Leveraging their independently - developed vertical - channel technology, they have successfully created a monolithically integrated complementary vertical - channel transistor structure (CVFET). This innovative structure surpasses the performance of the traditional complementary field - effect transistor architecture (CFET).

The CVFET adopts a dual - side technique that is fully compatible with CMOS manufacturing processes. Through a two - step epitaxial process, it precisely controls the thickness of the nanosheet channel and the gate length. This enables the vertical stacking and self - aligned integration of n - type and p - type nanosheet transistors, which is a key advancement in transistor design.

In terms of electrical characteristics, the CVFET shines brightly. For the upper and lower devices, it boasts subthreshold swings of 69 mV/dec and 72 mV/dec respectively. The drain - induced barrier lowering values are 12 mV/V and 18 mV/V. Moreover, the current on/off ratios reach 3.1×10⁶ and 5.4×10⁶. These excellent electrical properties make it a promising candidate for future electronic devices.

When it comes to the CMOS inverter based on the CVFET, it also shows remarkable performance. At a 1.2 V supply voltage, it achieves a gain of 13 V/V. At an operating voltage of 0.8 V, the high - level and low - level noise margins are 0.343 V and 0.245 V respectively. These results indicate its potential in high - performance electronic circuits.

The related research findings have been published in IEEE Electron Device Letters, which is a well - respected journal in the field of electronics, further validating the significance of this research.