Google Cloud is extending its eighth-generation Tensor Processing Unit (TPU) portfolio with two new systems, TPU 8tx and TPU 8i Max, targeting hardware-enforced confidential computing and memory-intensive AI inference. The TPU 8tx pairs Google’s custom AI accelerators with fifth-generation AMD EPYC host processors, combining CPU-based security capabilities with specialized AI compute. TPU 8i Max integrates two TPU 8i chips into a single package to increase compute resources, on-chip SRAM and high-bandwidth memory bandwidth. Announced November 9, the two designs expand Google’s eighth-generation portfolio to four specialized systems in 2026.

The TPU 8tx targets enterprises and government organizations handling sensitive data and proprietary AI models. AMD EPYC hosts handle workload orchestration, data preparation and communications with TPU accelerators. AMD Secure Encrypted Virtualization (SEV) contributes to a hardware-rooted security architecture extending protection to connected accelerators. Using TPU 8t silicon with Google’s Boardfly interconnect, TPU 8tx delivers up to twice as low latency as TPU 8t with a near-zero confidential-computing performance penalty, according to Google. The design also supports fine-tuning and reinforcement learning using private data.

TPU 8i Max targets workloads using large context windows and multiple cooperating AI agents. Its dual-chip package doubles compute, SRAM and HBM bandwidth relative to TPU 8i, according to Google, while occupying the existing rack footprint. Together, the announcements highlight the convergence of server CPUs, proprietary accelerators, packaging, high-bandwidth memory and confidential computing in hyperscale infrastructure. Google did not disclose pricing or a general availability date in its announcement.

The architecture also brings new technical capabilities into Google’s AI Hypercomputer software stack. For TPU 8tx, AMD says the system verifies an accelerator’s identity and security configuration before granting access to protected memory, with encrypted data transfers and hardware isolation extending security across CPU and TPU processing. For memory-intensive inference, Google’s new open-source TPU Sync software establishes a model-state layer spanning accelerator HBM, host DRAM, shared storage and data center networking. It uses asynchronous direct memory access (DMA) to move KV caches and model weights, supporting disaggregated prefill/decode processing and reinforcement learning. Google reports more than 90% lower KV-cache transfer latency in selected internal tests, although these results were obtained on Ironwood hardware rather than the newly announced TPU 8i Max.

“By pairing 5th Gen AMD EPYC processors with our 8th-generation TPU architecture inside the AI Hypercomputer, we are bringing hardware-enforced confidential computing to cloud TPUs for the first time.”

— Mark Lohmeyer, Vice President and General Manager, AI and Computing Infrastructure, Google Cloud, in AMD’s November 9 announcement.

Analysis: AI Accelerators Increasingly Depend on CPU and System Architecture

The AMD-Google collaboration illustrates the continuing role of general-purpose server processors in hyperscale systems built around custom AI accelerators. TPUs execute the specialized tensor operations; CPUs coordinate data preparation, orchestration, security and software execution. The TPU 8tx configuration extends AMD EPYC’s role into Google’s proprietary accelerator infrastructure.

Confidential computing moves the protection boundary beyond conventional encryption at rest and in transit. AMD SEV provides host-side hardware capabilities; Google’s implementation extends the architecture to attached TPUs and communications between components. The announcement does not supply an independent security certification or customer deployment benchmarks.

The TPU 8i Max addresses a different constraint: memory bandwidth and capacity pressure from long-context inference, KV caches and coordinated agents. Two TPU 8i chips in one package increase compute and memory resources without a wholly new silicon design. Google also announced supporting software, including TPU Sync to manage model state across HBM, host DRAM, shared storage and networking.

The TPU chronology shows a progression from inference ASICs to interconnected, liquid-cooled training systems, then to optical switching and workload-specialized configurations. Rather than replacing host CPUs, Google’s TPU program integrates them with accelerator packages, networking and security architecture.

Google’s TPU Development Timeline: 2015–2026

The progression from Google’s first inference accelerator to its eighth-generation systems demonstrates a shift from chip-level optimization to integrated AI infrastructure. The following timeline is presented newest first.

Across the generations, the most significant changes involve growing TPU pod scale, optical networking, cooling, memory bandwidth and, most recently, confidential computing. The eighth-generation lineup illustrates Google’s strategy of adapting a common silicon foundation to different AI workloads.