The U.S. Department of Commerce signed a letter of intent Wednesday with GlobalFoundries for a $300 million award from its CHIPS Research and Development Office — federal backing designed to pull silicon photonics, the technology that moves data using light instead of electrical signals, out of the research pipeline and into high-volume American manufacturing. The announcement sent GFS shares rising roughly 9.5% in pre-market trading and drew endorsements from every major AI hardware maker, a breadth of industry support that signals just how acutely the semiconductor ecosystem feels the pressure of a data-movement bottleneck that copper alone can no longer solve.

The award, which remains subject to negotiation before it becomes a binding commitment, will fund development of next-generation silicon photonics wafer technologies, novel optical materials, and advanced packaging — including a technique called 3D hybrid bonding — that GlobalFoundries says are prerequisites for bringing near-packaged and co-packaged optical architectures to production scale in the United States.

Why Copper Walls Off at AI Scale

Every AI training cluster is, at its core, a data-movement problem. Processors sit idle if they cannot exchange parameters, gradients, and activations fast enough to stay synchronized — and the copper interconnects that have handled this traffic for decades are running out of physics. At terabit-per-second data rates, copper links require increasingly aggressive equalization and retiming that consume power, add latency, and scale poorly as cluster sizes grow. The gap between what AI workloads demand and what copper can deliver is widening faster than engineers can engineer around it.

"The bottleneck in AI infrastructure is shifting from compute to connectivity — the ability to move data between and within systems without letting bandwidth or power constraints limit performance," said Chris Koopmans, President and Chief Operating Officer at Marvell, in a statement accompanying Wednesday's announcement. AMD CTO and EVP Mark Papermaster framed the same problem at the system level: "As AI systems scale, moving data efficiently is as critical as increasing compute performance."

Silicon photonics offers a path out of the bottleneck. By transmitting data as pulses of light through microscopic waveguides etched directly into silicon using standard CMOS-compatible fabrication processes, the technology delivers substantially higher bandwidth per unit of power than electrical signals. The silicon-on-insulator platform that makes this possible allows optical and electronic components to coexist on the same chip, drawing on four decades of silicon manufacturing infrastructure to do it affordably at scale.

NVIDIA founder and CEO Jensen Huang described the stakes plainly: "Rebuilding our supply chains is critical to the new industrial revolution. Scaling US manufacturing requires advances across chips, networking, optics, software, and manufacturing. Silicon photonics is essential to that future," Huang said in the official announcement.

How Co-Packaged Optics Actually Works — and Where It Breaks Down

The $300 million will build directly on GlobalFoundries' SCALE™ platform — Silicon Photonics Co-Packaged Advanced Light Engine — which targets 400 gigabits per second (Gb/s) data-transfer speeds and up to five times greater energy efficiency compared with current pluggable optical transceivers. The architecture at the center of this work, called co-packaged optics (CPO), places the optical engine directly alongside the AI processor or switch ASIC in a single package rather than running signals across a circuit board to a separate pluggable module, as explained in the press release.

In practice, this means eliminating the digital signal processing (DSP) retimer that conventional pluggable transceivers require, reducing the electrical path between the optical and electronic components to a few millimeters, and enabling bandwidth aggregation between 1.6 and 6.4 terabits per second per switch tile. NVIDIA's Quantum-X InfiniBand and Spectrum-X Ethernet switches have already deployed this architecture in production, reporting a 5x power efficiency gain over pluggable alternatives and a 5x improvement in sustained application runtime.

The mechanism that enables GF's version of this integration is 3D hybrid bonding — direct copper-to-copper bonding of the photonic integrated circuit (PIC) and electronic integrated circuit (EIC) at the die level, achieving sub-10-micron interconnect pitch without the solder bumps that conventional packaging requires. It is that bonding capability, GF CTO Gregg Bartlett emphasized, that positions the company to bring near-packaged and co-packaged architectures to high volume from U.S.-based fabs.

The technology, however, carries real engineering constraints that distinguish it from pluggable optical transceivers. When a CPO assembly fails, operators typically must replace the entire switch rather than swapping out the failed module — a serviceability burden that can mean hours of downtime rather than minutes. The heterogeneous integration of CMOS electronics, silicon photonics components, and III-V laser materials introduces multiple yield loss points during manufacturing; defects at any stage can write off the entire assembly because reworkability is severely limited. CPO testing requires simultaneous optical and electrical infrastructure, angstrom-scale fiber alignment tolerances, and active thermal management — capabilities the industry's existing high-volume test infrastructure was not designed to provide at scale.

As of early 2026, industry analysts projected CPO would not ship in volume until 2027 at the earliest, and the supply chain standards governing interoperability across vendors remain unresolved.

A Supply Chain Problem Washington Is Treating as a National Security Problem

The supply chain geography that makes this award strategically important has been years in formation. The existing ecosystem for silicon photonics and advanced optical packaging is heavily concentrated outside the United States, with major players including Taiwan's TSMC and Israel's Tower Semiconductor controlling significant manufacturing capacity. Wednesday's award is part of the Trump administration's broader effort to redirect CHIPS Act research funding toward technologies where U.S. dependency on foreign suppliers is viewed as a strategic vulnerability, consistent with prior commitments of $150 million for semiconductor manufacturing equipment and $2 billion for quantum computing, as reported by Reuters.

Bill Frauenhofer, Executive Director for Semiconductor Innovation and Investment at the Department of Commerce, made the framing explicit: "Accelerating R&D for domestic photonics capabilities and advanced packaging provides American industry the extreme bandwidth and energy efficiency to scale complex AI workloads securely and rapidly," he said in the official announcement.

Tower Semiconductor, GF's primary silicon photonics rival, committed $3 billion to expanding its silicon photonics and silicon germanium manufacturing capacity in Japan in July 2026, backed by approximately $1 billion from Japan's Ministry of Economy, Trade and Industry — a move that materially widened Tower's production lead in certain photonic integrated circuit segments. GF currently has three active patent infringement claims pending against Tower involving specialty process technologies. Wednesday's CHIPS R&D award is, in part, a public-sector counter-move in the same competition.

As a separate but structurally related dimension of the award, the Department of Commerce will receive an equity stake in GlobalFoundries representing approximately 1% of the company's ownership as of the date of the agreement — giving American taxpayers a direct financial interest in GF's growth should the program succeed.

Industry Endorsements Signal Ecosystem-Wide Urgency

The breadth of industry support accompanying Wednesday's announcement is uncommon even by CHIPS Act standards. Cisco President and Chief Product Officer Jeetu Patel emphasized the network dimension: "As AI infrastructure scales, moving data efficiently is becoming as important as compute itself," he said in the official announcement. Corning Chairman and CEO Wendell P. Weeks linked GF's photonics investment to the materials innovation layer his company supplies: "Meeting these demands will require innovation across the ecosystem from advanced materials and optical components to silicon photonics and packaging."

Meta VP of Engineering Yee Jiun Song highlighted the multi-supplier rationale that makes domestic U.S. capacity strategically valuable to hyperscalers: "We believe that a multi-supplier, geographically diverse ecosystem produces the best technical innovations and the most scalable high-volume supply chains, and investing in U.S. manufacturing capacity is a crucial component in achieving this goal." Microsoft's Rani Borkar, President of Azure Hardware Systems and Infrastructure, and Lumentum CEO Michael Hurlston both endorsed the investment in separate statements, each citing bandwidth and energy efficiency demands from AI workload scaling as the structural driver.

Taken together, the endorsements represent an industry consensus that silicon photonics at U.S. scale is not optional infrastructure — it is the next mandatory layer of AI buildout.

GF's CHIPS Track Record and Revenue Targets

Wednesday's photonics LOI is not GlobalFoundries' first engagement with CHIPS Act funding. The company secured up to $1.5 billion in direct CHIPS Act awards in November 2024, funding directed toward expanding and modernizing its fabrication facilities in New York and Vermont and advancing packaging capabilities — a process that took approximately nine months from the preliminary memorandum of terms signed in February 2024 to the final award agreement. Silicon photonics was explicitly named as a target technology in that earlier tranche.

The company set itself a commercially ambitious timetable alongside the announcement: more than doubling its silicon photonics revenue in 2026 and reaching an annualized run rate above $1 billion by the end of 2028. GF also reported Q1 2026 revenue of $1.634 billion, with non-IFRS diluted earnings per share of $0.40, beating analyst expectations, as covered in the TechTimes quantum foundry report.

One footnote from the company's recent compliance history bears noting. In November 2024, the Commerce Department's Bureau of Industry and Security fined GF $500,000 for shipping legacy semiconductor wafers valued at approximately $17.1 million — across 74 separate shipments — to SJ Semiconductor, an affiliate of China's SMIC that appeared on the U.S. Entity List. GF voluntarily disclosed the transactions, characterized them as a data-entry error made before the entity listing, and cooperated with investigators; Commerce reduced the penalty significantly and did not pursue further action. The Commerce Department's decision to award GF a $375 million quantum manufacturing LOI in May 2026 and this photonics LOI today indicates the agency considers the matter closed.

What Is the Relationship Between Silicon Photonics and Quantum Computing?

Wednesday's silicon photonics LOI exists alongside a companion quantum award announced in May 2026. The Department of Commerce signed a separate letter of intent to award GF up to $375 million to manufacture quantum processor units across multiple qubit modalities, including silicon photonics, superconducting, and trapped-ion approaches, under a new platform called Quantum Technology Solutions. The two awards share a technological spine: silicon photonics is a core enabling technology for both AI optical interconnects and quantum hardware — photonic qubits, photonic interconnects between quantum modules, and classical control logic all draw on the same silicon photonics manufacturing foundation.

The quantum partners GF assembled for that program — PsiQuantum, Quantinuum, Diraq, Equal1, and Microsoft Quantum — each require silicon photonics manufacturing infrastructure to scale their hardware, as reported by CryptoBriefing.

What Comes Next

A letter of intent is not a final award. As GF's own recent history demonstrates, the path from LOI to binding agreement involves additional negotiation, due diligence, and compliance processes; the 2024 $1.5 billion direct award took roughly nine months from preliminary agreement to final execution. No timeline for converting Wednesday's LOI into a binding commitment was disclosed.

For investors, the next concrete milestone is GF's Q2 2026 earnings call, scheduled for August 5, 2026, at 8:30 a.m. ET — one week from today — when the company is expected to provide updated revenue guidance and commentary on its silicon photonics commercial pipeline alongside the full financial results.

For the broader semiconductor industry, the signal is structural: Washington is treating optical data-movement infrastructure with the same urgency it previously applied to advanced logic and memory chips. As AI workloads push past what copper interconnects can carry — in both bandwidth and energy terms — the federal commitment to building that optical manufacturing capability domestically, and the industry alignment behind it, has now been formalized in terms both sides can take to a balance sheet.

Frequently Asked Questions

What is silicon photonics, and why does it matter for AI?

Silicon photonics is a technology that transmits data using pulses of light rather than electrical signals, encoding information in photons that travel through microscopic silicon waveguides fabricated with standard chip-manufacturing equipment. In AI data centers, the appeal is thermodynamic: light-based interconnects deliver significantly higher bandwidth per watt than copper, eliminating the signal equalization and power overhead that limit copper's performance as AI cluster sizes grow. At the speeds that next-generation AI training and inference clusters require — 400 Gb/s and above — copper interconnects require increasingly elaborate and energy-intensive retiming circuits; optical interconnects eliminate that layer entirely.

What is co-packaged optics, and what are its limitations?

Co-packaged optics integrates the optical engine — the components that convert electrical signals to light and back again — directly into the same package as the AI processor or switch ASIC, rather than housing it in a separate pluggable transceiver. This eliminates the DSP retimer, shortens the electrical path to millimeters, and cuts power consumption by up to five times compared with pluggable optical modules. The tradeoff is serviceability: if the optical engine fails in a co-packaged design, the entire switch typically must be replaced rather than just the failed module — a repair that takes hours rather than minutes. Manufacturing yield is also more challenging because the heterogeneous integration of silicon, III-V laser materials, and CMOS electronics creates multiple points where a defect can write off the entire assembly. Industry analysts projected CPO would not ship in volume until 2027.

Is the $300 million award confirmed, or is it conditional?

As of Wednesday, the award exists as a letter of intent — a formal statement of expected terms from the U.S. Department of Commerce, but not a binding agreement. Final execution requires additional negotiation, due diligence, and compliance verification. GF's 2024 $1.5 billion direct CHIPS Act award took approximately nine months from preliminary memorandum to binding agreement. No timeline for converting this LOI was disclosed.

How does silicon photonics connect to quantum computing?

Silicon photonics serves both classical AI infrastructure and quantum hardware. The same fabrication platform that produces optical waveguides for AI data center interconnects is used to manufacture photonic qubits, photonic interconnects between quantum modules, and cryogenic control components. GlobalFoundries' separate $375 million quantum LOI, signed in May 2026, covers silicon photonics, superconducting, and trapped-ion qubit manufacturing — meaning GF is building a single domestic manufacturing base that underpins both the current AI buildout and the longer-term quantum computing roadmap simultaneously.