The TSMC logo is displayed at the Taiwan Semiconductor Manufacturing Company branch and Innovation Museum, highlighting the company branding and signage inside and outside the site in Hsinchu, Taiwan, January 27, 2026. Jimmy Beunardeau/Getty Images

Taiwan Semiconductor Manufacturing Company delivered the most profitable quarter in its history on Thursday, reporting second-quarter 2026 revenue of $40.2 billion — a 36% jump year over year — and raising its full-year growth target to above 40%, the second upward revision this year, as artificial intelligence continued to consume silicon at a pace that far outstrips the industry's ability to build the factories needed to keep up.

The results, reported at an earnings conference in Taipei, surpassed analyst expectations across every key metric and confirmed what investors and AI laboratory researchers have been debating for months: the infrastructure spending cycle that many expected to plateau in 2026 has instead accelerated. Net profit surged 77.4% to NT$706.56 billion, setting a new single-quarter record and extending TSMC's streak of consecutive double-digit profit growth to nine quarters. Gross margin climbed to 67.7%, edging above the company's own guidance ceiling and reflecting the pricing power that comes from holding roughly 73% of the global advanced foundry market with no credible near-term challenger for the customers that matter most.

"Our conviction in the multi-year AI megatrend remains very high," TSMC Chairman and CEO C.C. Wei told analysts on the call.

High-Performance Computing Now Drives Two-Thirds of TSMC Wafer Revenue

The shift in TSMC's revenue mix across this earnings cycle is the clearest single measure of how thoroughly AI has restructured global semiconductor demand. High-Performance Computing — the segment anchored by AI accelerators for cloud data centers — rose 20% sequentially in a single quarter and now accounts for 66% of total wafer revenue. Smartphones, which generated the largest share of TSMC's revenue as recently as 2022, fell to 22%, according to TSMC's Q2 2026 investor relations data.

Advanced process nodes drove nearly all of that shift. TSMC's 3-nanometer process (N3) accounted for 30% of wafer revenue in the quarter, with the adjacent 5-nanometer node contributing 33%. Combined with 7-nanometer production, advanced nodes at 7nm and below represented 77% of all wafer revenue — a figure that illustrates both how far chip manufacturing has come and how concentrated the value has become at a single company's leading edge.

William Li, a senior analyst at Counterpoint Research, said before the results that AI infrastructure investment "remains exceptionally strong despite macro uncertainty" and that demand for AI GPUs, AI ASICs, and advanced packaging "continues to exceed expectations." Simon Chen, a principal analyst at Omdia, characterized fears about overstretched AI valuations as "overstated," arguing that the demand is "structural, backed by massive, tangible capital expenditures from hyperscalers."

What the 2nm Ramp Actually Costs — and What It Buys

The quarter also marked a milestone whose financial cost is visible in the forward guidance: TSMC's 2-nanometer process node (N2) made its first meaningful commercial revenue contribution, accounting for 3% of wafer revenue in Q2 as the company completed the transition from engineering samples to paying production volume, as reported in TSMC's Q2 2026 earnings release.

N2 represents a fundamental architectural break from every TSMC process node that preceded it. Every chip TSMC has ever produced for commercial customers — from its earliest 500nm processes through the 3nm node that manufactures NVIDIA's current Blackwell GPUs — used the same basic transistor design: the FinFET, a vertical silicon fin with a gate electrode wrapped around three sides. N2 replaces this with a gate-all-around nanosheet transistor, in which three horizontal silicon ribbons are fully encircled by the gate on all four sides, as IEEE Spectrum's coverage of TSMC's IEDM presentation explains.

The engineering significance is not cosmetic. In a FinFET, the three-sided gate leaves one side of the channel exposed, creating a leakage pathway — a current that flows even when the transistor is supposed to be off — that grows worse as the fin shrinks. Nanosheet's four-sided gate eliminates that pathway, which is why TSMC's N2 delivers 15% faster switching speed, or 30% lower power consumption at the same speed, compared to N3 — while increasing transistor density by more than 15%. On-chip memory density, a longstanding bottleneck in processor design, improves by 11% in N2 versus 6% in the prior generation, a result that TSMC's vice president of advanced R&D attributed specifically to the gate-all-around architecture: the new transistor structure "harvests the intrinsic gain of going to gate-all-around."

The tradeoff is a steeper yield curve. Building a new transistor geometry from scratch — one that requires stacking horizontal silicon ribbons in precise, reproducible arrangements — takes longer to yield consistently than extending a FinFET process that has been optimized over more than a decade. CFO Wendell Huang told analysts that the steep production increase expected in the second half of 2026 will dilute gross margins by roughly 3 to 4 percentage points before scale efficiencies take hold. For Q3 2026, TSMC guided revenue of $44.6 billion to $45.8 billion — approximately 37% year-over-year growth at the midpoint — with gross margins expected to ease to 65% to 67%.

What Is CoWoS, and Why Has It Become AI's Most Critical Bottleneck?

TSMC's CoWoS advanced packaging platform — abbreviated from Chip-on-Wafer-on-Substrate — is the technology that physically integrates AI chips with high-bandwidth memory in the dense configurations that large language model training and inference require. It is also, as of this quarter, operating at full capacity with lead times extending 52 to 78 weeks.

Understanding why CoWoS is sold out requires understanding what it does that conventional packaging cannot. In a standard chip package, a processor connects to memory through a circuit board, with electrical signals traveling millimeters and losing speed and energy along the way. CoWoS places the AI logic die and multiple stacks of high-bandwidth memory side by side on a silicon interposer — a flat silicon wafer that itself has been fabricated with dense copper interconnects called Through-Silicon Vias. The inter-die signals travel microns through silicon rather than millimeters through board material, increasing memory bandwidth from roughly 1 terabyte per second (GDDR6) to over 3 terabytes per second (HBM3E via CoWoS). The NVIDIA H100, H200, and every generation of the Blackwell GPU depends on CoWoS for this bandwidth. So does every AMD MI-series accelerator and every custom AI chip Google, Amazon, and Microsoft build for their data centers, as SemiconductorX's CoWoS architecture overview and WikiChip's documentation detail.

The constraint is structural, not temporary. Manufacturing a CoWoS interposer requires a dedicated silicon fabrication step — the interposer is itself a wafer, produced in TSMC's advanced packaging fabs with its own process steps, equipment, and yield curve. There is no merchant market for CoWoS interposers or assembled CoWoS modules. Every N2 or N3 AI accelerator chip that exits TSMC's wafer fabs must still pass through CoWoS assembly before it can ship to a customer. And as AI chips get denser — as N2's improved transistor count enables more compute per die — the number of HBM stacks each chip requires tends to increase, meaning each generation of AI accelerator places greater, not lesser, demand on CoWoS capacity.

Wei acknowledged that the packaging bottleneck is now constraining customer growth, and said TSMC welcomes competitive packaging offerings from rivals as a means of relieving pressure on its own capacity rather than viewing them as a threat. Competitors including Intel (EMIB + Foveros) and Samsung have equivalent architectures, but independent assessments place them two to three years behind TSMC in production volume and yield for AI accelerator workloads.

$265B Arizona Commitment Locked In; CapEx Raised Again

Beyond the quarter's operating results, the most consequential disclosure was TSMC's decision to raise its 2026 capital expenditure budget to $60 to $64 billion, up from a prior guidance range of $52 to $56 billion — an increase of between $4 billion and $12 billion in a single quarter, as CFO Wendell Huang announced on the call. Between 70% and 80% of that spending will flow to advanced process technologies, with the remainder split between specialty nodes and advanced packaging.

Wei went further on the multi-year trajectory: "The CapEx in the next three years will be even more significantly higher than the past three years."

The company also announced an additional $100 billion investment in its Arizona manufacturing operations, encompassing approximately four or more additional fabs covering both front-end wafer fabrication and back-end advanced packaging for 2-nanometer-class and below technologies. Total committed investment in Arizona now stands at approximately $265 billion, up from the $165 billion commitment announced in March 2025. Wei said TSMC is moving "as fast as possible" given the scale of the supply shortfall, per Tom's Hardware's reporting on the announcement.

That Arizona total represents the largest foreign direct investment in a greenfield manufacturing project in American history. The expansion is simultaneously TSMC's most ambitious geographic commitment and its most visible acknowledgment that supply constraints, rather than demand uncertainty, are the binding limit on its own growth.

Agentic AI Opens a Second Demand Channel

Management flagged a development that has not yet fully registered in AI infrastructure discussions: the rise of agentic AI is changing the composition of data center demand in a way that benefits TSMC beyond its existing AI accelerator business.

In the chatbot era — the period from 2022 through roughly mid-2025 — AI demand was dominated by GPU-centric model training and inference, with CPUs serving brief orchestration bursts. In agentic AI architectures, AI systems autonomously execute multi-step tasks: browsing, writing, coding, communicating, and making decisions with minimal human prompting. These workloads require sustained, always-on CPU processing for tool calling, memory management, API orchestration, and multi-step reasoning loops. Independent analysis from TrendForce suggests agentic applications may require four times as many CPU cores per gigawatt of data center power as training-era infrastructure — shifting the CPU-to-GPU server deployment ratio from the historical 1:8 toward 1:1 for some workloads.

TSMC manufactures leading chips using every major CPU architecture — x86 (Intel, AMD), Arm, and RISC-V — and Wei said the company is already working with CPU customers to allocate capacity for agentic AI applications. This creates what TSMC characterizes as incremental silicon demand layered on top of the existing GPU-accelerator wave, rather than a substitution for it.

TSM Shares Hold Near Flat as Investors Weigh Spending Plans

TSM shares closed the regular session at $419.48, essentially unchanged from the prior session, before slipping approximately 1.55% in after-hours trading to around $412.99. Analysts attributed the measured response to investor focus on the heavier capital spending plan and the expected near-term gross margin compression from the N2 ramp — a rational response to a quarter in which the revenue and profit numbers were stellar but the forward guide on margins flagged a temporary step-down.

On competitive pressure from Samsung Foundry and Intel's foundry business, Wei was characteristically direct: technology leadership, manufacturing execution, and customer trust are the only durable advantages in the foundry business. He noted that replicating TSMC's manufacturing position requires roughly five years of sustained effort per process generation.

How TSMC's Results Function as the AI Buildout's Real-Time Signal

TSMC's quarterly results carry analytical weight that extends well beyond any single company's financial performance. Because TSMC manufactures the GPU dies inside virtually every AI accelerator from NVIDIA and AMD, as well as custom AI silicon for Google, Apple, Amazon, and Microsoft, its revenue trajectory provides a cleaner real-time read on actual AI chip purchasing behavior than the capital expenditure announcements of cloud providers — which capture commitments, not deliveries.

By that measure, Thursday's report is unambiguous. Revenue growth accelerated to 36% year over year from 35% the prior quarter. The full-year outlook rose from above 30% to above 40%. The company raised its CapEx budget twice in a single year. And its CEO extended his previously stated five-year AI semiconductor compound annual growth rate estimate — already described as "in the mid-to-high 50s" — with the assessment that the underlying trend is "stronger and stronger," per the Q2 earnings call.

For investors, AI laboratory researchers, and enterprise technology buyers who need to plan around chip availability, the message from Thursday's Taipei earnings conference is direct: the silicon needed to power the AI buildout remains, for now, the binding constraint on everything else — and the packaging step that integrates that silicon with memory is an even tighter constraint than the silicon itself.

Frequently Asked Questions

What is CoWoS packaging, and why does TSMC say it is fully booked?

CoWoS — Chip-on-Wafer-on-Substrate — places an AI processor and multiple stacks of high-bandwidth memory side by side on a silicon interposer, connecting them through microscopic copper vias rather than circuit board traces. This arrangement increases memory bandwidth by roughly three to nine times compared to conventional packaging, which is what allows NVIDIA, AMD, and major cloud AI accelerators to run large language models efficiently. CoWoS assembly runs captive at TSMC — there is no alternative market for the interposers — and manufacturing an interposer requires its own dedicated silicon fabrication step. As AI chips get denser, each chip requires more memory stacks, which means each new chip generation demands more CoWoS capacity. That is why TSMC's management describes the packaging bottleneck as structural rather than temporary: it gets harder to solve as AI chips advance, not easier.

How does TSMC's 2nm process differ from its 3nm node?

Every chip TSMC manufactured through its 3nm (N3) node used a FinFET transistor — a vertical silicon fin with a gate electrode wrapped around three sides. TSMC's 2nm (N2) switches to a gate-all-around nanosheet transistor, in which three stacked horizontal silicon ribbons are each fully encircled by the gate electrode. The four-sided gate eliminates the current leakage pathway that degrades FinFET performance at small scales. The result: N2 is 15% faster, or 30% more energy-efficient at the same speed, compared to N3, with over 15% better transistor density. On-chip memory (SRAM) density improved by 11% in N2, compared to a 6% improvement when N3 was introduced — and TSMC engineers attribute that outsized gain directly to the gate-all-around architecture.

Is the AI chip shortage getting better or worse in 2026?

TSMC's Q2 results suggest the supply gap is not narrowing. N3 capacity is described by management as substantially oversubscribed; CoWoS packaging lead times extend 52 to 78 weeks; and the company raised its capital spending budget by up to $12 billion in a single quarter while signaling that the following three years will require even higher spending. The $265 billion total Arizona commitment and new fabs under construction in Taiwan and Japan are responses to a supply shortfall that TSMC's CEO has acknowledged will extend well beyond the current planning horizon. The constraint is not customer demand — it is the physical infrastructure to manufacture the silicon, package it with memory, and ship it at the scale that cloud data center buildouts require.

What does TSMC's earnings result mean for AI software and product timelines?

TSMC's results confirm that the bottleneck in AI capability deployment is physical silicon availability, not algorithms, funding, or software. AI laboratories building the next generation of frontier models depend on access to NVIDIA, AMD, and custom AI accelerators — all of which are manufactured by TSMC. If CoWoS capacity is the binding constraint above even wafer fab capacity, and lead times are 52 to 78 weeks, then a model that requires a new generation of AI hardware will take at least that long to acquire the compute cluster to train it, regardless of how ready the software is. Companies and research teams that have not already secured capacity allocations are competing for a constrained resource — and TSMC's CapEx raise suggests the gap will not close until well into 2027 or 2028 at the earliest.