Advanced Micro Devices introduced an open rack reference design at the Open Compute Project Global Summit on Monday that embeds a software model router into the infrastructure layer — routing each AI agent's model calls to either a cloud-hosted frontier system or a local open-source model based on cost and latency, rather than defaulting every request to an expensive GPU cluster.

The design, named Helion, is AMD's first rack-scale architecture built explicitly around agentic AI workloads, and it debuted alongside a production milestone confirmation for the company's Helios 72-GPU rack and a first public showing of silicon for the next-generation EPYC Verano server processor. AMD published the full Helion announcement on its newsroom, with the press release timestamped October 12, 2026.

AMD Chair and CEO Dr. Lisa Su framed the announcements around what she called "the heterogeneous data center" — an infrastructure model where CPUs, GPUs, and other accelerators serve separate workload roles rather than competing for dominance within a single architecture. In the OCP keynote recap published by AMD, Su stated from the keynote stage in San Jose: "There are going to be a lot of accelerators out there. It's not one-size-fits-all. It's not one company has all the best parts."

The shift from chatbot inference to agentic AI changes what data center hardware actually does. In a standard LLM deployment, one CPU supports four to eight GPUs; in an agentic configuration, CPUs absorb the orchestration layer — routing tool calls, querying databases, triggering external APIs, enforcing security policy — while GPUs remain focused on model inference alone.

AMD's agentic AI infrastructure blog documents this structural shift as moving toward a 1:1 CPU-to-GPU ratio. Helion is AMD's architectural answer to that structural change: a rack blueprint that treats orchestration and inference as separately scalable resources rather than a single pooled compute environment.

Helion: AMD's Open Blueprint for Agentic AI

Helion is a published blueprint, not a product AMD sells directly. AMD intends to contribute it to the OCP community, allowing OEMs, ODMs, and hyperscalers to design and manufacture their own systems against a shared specification—extending the open-hardware philosophy AMD established with Helios, but aimed at orchestration-heavy workloads rather than frontier-scale inference.

The AMD newsroom page covering Helion's OCP contribution plans notes the blueprint will be made available to the community for further development and adoption. The chassis is a 21-inch, 44-OpenU enclosure built to the OCP Open Rack V3 specification. Six additional standards layer into the design: DC-MHS for host processor modules, DC-SCM for platform management and security, HPRv2 for power shelves, OCP NIC 3.0 for networking, and Caliptra as the silicon root of trust.

The blueprint specifies two primary system configurations. The first is a CPU-only rack powered by sixth-generation EPYC "Venice" processors, housing up to 32,768 CPU cores per enclosure. This configuration targets hyperscale operators, neoclouds, and sovereign AI deployments that need dedicated agent-execution capacity connected to separate inference infrastructure over the network.

The second is an enterprise all-in-one configuration that pairs EPYC CPU blades with AMD Instinct MI350P GPU inference nodes, supporting up to 16 MI350P GPUs per rack according to AMD's announcement. Both configurations support air cooling and direct liquid cooling.

The Model Router: Where Agent Cost Optimization Happens

The feature that most distinguishes Helion from a conventional OCP rack is the integrated model router embedded in its software stack. Rather than funneling every model request to a single expensive frontier system, the router analyzes incoming agent calls and dispatches each to the most cost-effective backend—a cloud-hosted frontier model for tasks requiring frontier-scale capability, or a locally hosted open-source model running within the rack for lower-complexity or latency-sensitive requests.

The AMD Helion announcement describes the router directing "agents' model calls across frontier and open-source models." The router operates at the model-request layer, distinct from packet routing or accelerator fabric switching.

Dan McNamara, AMD Senior Vice President for server solutions, told Fierce Network that internal testing with the model router produced a 43 percent reduction in token costs alongside response times up to three times faster for workloads shifted to local inference. The cost savings are structural: requests dispatched to a locally-hosted open-source model incur zero marginal API cost, so the router's primary economic lever is shifting routine agent calls away from per-token frontier API pricing rather than improving throughput on any individual request.

AMD positioned the router as the mechanism that lets operators scale CPU orchestration resources independently of GPU inference resources—buying more CPU capacity for agent execution without proportionally expanding GPU inventory.

Charlie Dai, principal analyst at Forrester, described the strategic implication of separating orchestration from inference at the infrastructure level: keeping accelerators focused exclusively on inference while CPUs absorb orchestration overhead should measurably improve GPU utilization.

The disaggregated approach is not unique to AMD — Intel and SambaNova have separately proposed a three-tier inference model that routes prefill, decode, and agent execution to different processor classes — confirming that separating inference stages by hardware type has become an industry-level pattern rather than a vendor-specific positioning claim.

Who Is Building Helion Systems?

AMD announced that Dell, Cisco, HPE, Lenovo, QCT, Supermicro, Wiwynn, and Hon Hai support the Helion reference design. The full Helion partner announcement at AMD's newsroom includes statements from all eight partners. Hon Hai Technology Group confirmed its involvement explicitly in a statement released via GlobeNewswire, citing its rack-level system integration and global manufacturing capabilities. Partner-built Helion configurations are planned to be available beginning November 2026.

Analyst firm NAND Research noted that AMD has not yet released published agent benchmark data quantifying Helion's rack-level performance claims, which will limit direct comparison against existing options until operators begin reporting production results. The November partner availability timeline is aggressive for a rack-scale architecture of this complexity, and the 43-percent cost-reduction figure from internal AMD testing has not been independently verified at a rack level across representative agentic workloads.

Helios: September Production Confirmed for Microsoft Azure

Alongside the Helion debut, Su confirmed that the Helios 72-GPU rack entered production shipments in September 2026, with volume ramp continuing through the fourth quarter and into the first half of 2027. The AMD OCP keynote recap confirms that "initial systems are installed and running at OpenAI, Meta, Microsoft and Oracle." Microsoft Azure was publicly identified as an early hyperscale recipient.

Helios is built around 72 AMD Instinct MI455X accelerators running the CDNA 5 architecture with HBM4 memory, paired with sixth-generation EPYC Venice CPUs and AMD Pensando networking in a single direct-liquid-cooled Open Rack Wide enclosure. The AMD Advancing AI 2026 newsroom confirms the full rack carries approximately 31 terabytes of HBM4 memory and targets around 2.9 exaflops of FP4 AI inference performance. Converge Digest's OCP floor coverage reports fully configured Helios racks at roughly $5.25 million per cabinet.

The production confirmation matters as context for Helion: together, Helios and Helion represent AMD's rack-level answer to the heterogeneous data center — a division of labor between GPU-centric frontier inference and CPU-centric agent execution, with the Helion model router positioned at the boundary to dispatch requests between them.

EPYC Verano First Silicon Shows at OCP With a Core Count Revision

Su brought physical Verano silicon to the OCP Summit keynote stage, marking the first public demonstration of the processor designed to serve as the host CPU backbone for agentic infrastructure. The AMD OCP keynote article confirms Su "displays a 6th Gen EPYC 'Verano' data center CPU during the opening keynote." Verano is part of the EPYC 9006 "LP" family — where LP denotes both LPDDR5X memory support and a low-power design emphasis — and is the first AMD EPYC processor to support LPDDR5X memory, delivered through SOCAMM2 modules. Like Venice, it is built on the Zen 6 architecture and TSMC's 2nm process node.

Verano runs on the SB1 socket, a BGA permanently-soldered design that eliminates the field-swappable CPU replacement that the SP7 socket used by the shipping Venice generation allows. Details on the SB1 socket BGA design trade-off were covered in TechTimes' October 10 analysis. The trade is made in favor of memory bandwidth: the 24-channel LPDDR5X memory subsystem approaches 2.9 terabytes per second of throughput, compared to approximately 1.2 TB/s on NVIDIA's Vera CPU — an advantage for agent-execution workloads that are memory-throughput-bound when managing many concurrent in-context operations. Verano connects to AMD Instinct MI500 GPU accelerators via xGMI at up to 112 gigabits per second.

The silicon demonstrated at OCP supported up to 192 cores, organized as six compute chiplets of 32 cores each, according to Converge Digest's reporting from the OCP floor. That figure represents a substantial upward revision from the 72-core platform AMD had previously disclosed in roadmap materials, and from the estimate TechTimes derived from a Dynatron cooler listing three days before the summit. AMD targets Verano production in the first half of 2027, where it will serve as the host CPU backbone for next-generation Helion racks.

AMD, NVIDIA, Google, and Meta Jointly Publish Open Data Center Specification

At the same summit, AMD, NVIDIA, Google, and Meta jointly published the Open Data Center Specification v0.7, a shared facility blueprint covering power architecture, cooling infrastructure, and physical layout for next-generation AI factory data centers. The specification gives equipment manufacturers, colocation providers, and hyperscalers a common foundation as AI data centers scale from megawatt deployments toward gigawatt campuses.

The four-way authorship reflects a shared conclusion among direct competitors that standardizing the facility layer benefits everyone, even as the compute layer remains fiercely contested: AMD, NVIDIA, Google, and Meta compete in AI chips, cloud capacity, and AI models simultaneously, yet all four published a shared facility specification. In a coordinated but separate announcement, Google, Meta, Microsoft, and NVIDIA published the OCP Grid Resilience Specification, which defines automated response protocols designed to restore near-full computational load within two seconds of a utility disturbance.

What Does Helion's Model Router Change for Data Center Operators?

The core claim from AMD's OCP presentations — that Helion enables independent CPU and GPU scaling — depends on the model router delivering in production deployments what it produced in AMD's internal testing. Patrick Moorhead, principal analyst at Moor Insights & Strategy, has described heterogeneous compute as "the necessary path forward" for AI infrastructure, a framing consistent with AMD's positioning but not a validation of Helion's specific implementation. No published agent benchmark data quantifying Helion's rack-level performance across representative workloads has been released, and the November 2026 partner availability timeline is aggressive.

What is already confirmed: Helios has cleared its production milestone and is shipping to customers including Microsoft Azure. The open-contribution model — publishing Helion as an OCP reference design rather than a proprietary appliance — lowers the barrier for operators wary of vendor lock-in and creates gravitational pull toward AMD's EPYC and Instinct ecosystem without requiring AMD to control every layer of the infrastructure stack. The near-term question is whether the OEM partner ecosystem can match the schedule, and whether AMD will release independent benchmark data before customers commit to a November deployment.

Frequently Asked Questions

What is the difference between Helion and Helios?

Helios is AMD's shipping 72-GPU rack designed for frontier-scale AI training and large-scale inference, built around 72 Instinct MI455X accelerators and now in production as of September 2026. Helion is a separate, OCP-standard open rack reference design aimed specifically at the CPU-intensive orchestration and tool-calling work that agentic AI adds on top of inference. The two platforms are designed to work together: Helion handles the agent execution layer, while Helios — or any other inference platform accessible over the network — handles the actual model inference. Helion is an open blueprint that OEM partners will manufacture; Helios is a shipping product. The AMD OCP keynote recap covers both announcements together and explains how the two platforms complement each other.

How does the Helion model router reduce token costs?

The model router embedded in Helion's software stack analyzes each incoming agent call and routes it to the cheapest backend capable of handling it adequately—either a cloud-hosted frontier model for tasks requiring maximum capability or a locally hosted open-source model within the rack for simpler or latency-sensitive requests. AMD's Dan McNamara told Fierce Network that internal testing showed a 43 percent token cost reduction and response times up to three times faster for workloads shifted to local inference. The savings are structural: requests dispatched to a local model incur zero marginal API cost, so the router's economic lever is shifting routine agent calls away from per-token frontier API pricing rather than improving throughput on any individual request. Operators who manage frontier API spend by routing at the infrastructure level, rather than at the application layer, have the largest cost-optimization opportunity.

What is the SB1 socket, and why does Verano use it instead of SP7 or SP8?

The SB1 socket is a permanently soldered BGA (ball grid array) design that AMD introduced with the EPYC Verano LP family. Unlike the SP7 and SP8 LGA sockets used by AMD's other Zen 6 server CPUs, SB1 solders the processor directly to the server board, eliminating field-swappable CPU replacement. TechTimes covered this socket design trade-off in detail on October 10. AMD accepts that operational trade-off to enable a 24-channel LPDDR5X memory subsystem capable of about 2.9 terabytes per second of bandwidth — compared to about 1.2 TB/s in NVIDIA's Vera CPU — which is the memory throughput agent-execution workloads require when running many concurrent in-context operations. NVIDIA made the same architectural choice with Vera, indicating that the bandwidth-versus-serviceability trade is becoming standard for AI-host CPUs.

When will Helion systems be available, and is AMD releasing any benchmark data?

Partner-built Helion configurations from Dell, Cisco, HPE, Lenovo, QCT, Supermicro, Wiwynn, and Hon Hai are planned to be available beginning November 2026, according to AMD's Helion announcement. AMD is contributing the Helion blueprint to the Open Compute Project as an open reference design rather than selling a proprietary AMD-branded rack, so buyers will purchase from OEM partners building against the shared specification. As of the OCP Summit announcement, AMD has not released published benchmark data quantifying rack-level performance claims under representative agentic workloads. NAND Research flagged this gap at the summit; operators evaluating Helion will need to wait for OEM availability or published independent results before making direct performance comparisons.