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JCET Granted Patent for 'Method for Fabricating a Packaging Structure and Chip Warpage Prevention Device'
2025-01-20 /
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Author：小编
JCET has recently been granted a patent titled 'Method for Fabricating a Packaging Structure and Chip Warpage Prevention Device' under authorization announcement number CN115101434B, announced on December 6, 2024 (Note: The original text mentioned December 10, which may be erroneous; the official announcement date of December 6 stands). The patent application was filed on July 21, 2022. This innovative patent significantly mitigates chip warpage during the reflow soldering process, minimizes the risk of soldering failures, and enhances the overall quality of 3D packaging soldering.
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