Recently, Hanxu Technology, a leading domestic enterprise specializing in MRAM (Magnetoresistive Random-Access Memory) in-memory computing inference chips, has officially announced the launch of its innovative uHBM® and uLPU™ inference computing architectures. For the first time, the company has fully disclosed its comprehensive product layout, which spans from chip die and single chips to modules and cabinets, covering the entire chain.

The uHBM® architecture ingeniously integrates Persistent MRAM with matrix-vector computing capabilities, enabling weight-resident computing. Its first-generation design boasts an impressive 24 TB/s In-Die Read Bandwidth, setting a new benchmark in the industry.

The uLPU™ product roadmap is designed to evolve from the uHBM® to the uLPU™-Rack, offering both edge-side and cloud-side solutions. The edge-side variant integrates four uHBM® units with an NPU (Neural Processing Unit), while the cloud-side version combines four uHBM® units with a uIO Die. Targeting embodied models like Qwen-VLA, the uLPU™ architecture aims to achieve edge-side Decode speeds exceeding 2000 Tokens/s, marking a significant leap in processing efficiency.

This groundbreaking architecture not only enhances Hanxu Technology's AI inference hardware industrialization system but also provides robust support for dedicated computing acceleration in critical fields such as drug development, scientific computing, and aviation logistics. With these advancements, Hanxu Technology is poised to make a substantial impact on the AI hardware landscape.