As ultra-high-speed wired transceivers and next-generation millimeter-wave communication technologies evolve toward data rates of 100 Gbps and above, the millimeter-wave band has become key to achieving ultra-large bandwidth transmission due to its ultra-wide continuous spectrum resources. However, in the millimeter-wave band, traditional phase-locked loop (PLL) architectures face physical and design bottlenecks: the quality factor of on-chip passive devices degrades with increasing frequency, leading to deterioration of phase noise in high-frequency voltage-controlled oscillators (VCOs). Meanwhile, the high-frequency clock division and phase detection processes introduce significant power consumption, and the gain of traditional phase detectors attenuates in the millimeter-wave band, weakening the loop's ability to suppress in-band noise. To overcome these bottlenecks, the Institute of Microelectronics of the Chinese Academy of Sciences, in collaboration with Tsinghua University and the University of Macau, has proposed a high-energy-efficiency, low-jitter millimeter-wave cascaded PLL chip architecture. This architecture innovatively integrates two key technologies: 'implicit second harmonic extraction' and 'fifth harmonic mixing phase detection.' In the first-stage fundamental frequency VCO, high-quality second harmonics are implicitly extracted to serve as the high-frequency reference source for the second stage. Simultaneously, a novel fifth harmonic mixing phase detection technique enables a 10-fold frequency multiplication of the fundamental output while keeping jitter degradation nearly negligible. Additionally, this architecture eliminates the high-power-consumption oscillator buffers and non-overlapping sampling clocks used in traditional millimeter-wave cascaded schemes, effectively removing the bottleneck of phase detector gain being limited by sampling capacitance, and significantly improving the energy efficiency and noise suppression capabilities of the frequency synthesizer. Based on the above technologies, the team implemented a V-band PLL clock chip using a 28nm CMOS process, with an output frequency covering 54–60 GHz, overall power consumption below 15mW, RMS integrated jitter better than 60fs, and a frequency-division-ratio-normalized jitter-power consumption figure of merit (FoMN) below −280dB, providing a forward-looking technical pathway for low-jitter millimeter-wave clock generation.