Recently, the research team headed by Professor Hu Yizhe from the School of Integrated Circuits at the University of Science and Technology of China (USTC) has achieved a significant breakthrough in the realm of high-speed Voltage-Controlled Oscillator (VCO)-based Analog-to-Digital Converter (ADC) chip research. The team introduced an innovative ADC architecture that leverages a resettable ring VCO, known as the R-RVCO-based ADC. This novel design successfully attains a remarkable sampling rate of up to 2.5 GS/s, effectively overcoming the performance limitations that traditional architectures face in high-speed applications.

By incorporating differential transfer characteristics, the proposed architecture effectively mitigates the phase noise integration effect, eliminating the need for an additional differentiator. Simultaneously, it circumvents quantization noise shaping within the Nyquist band, thereby enhancing the Signal-to-Noise Ratio (SNR) by approximately 3 dB. Furthermore, the architecture obviates the necessity for a digital differential module, thereby augmenting the system's resilience to flip-flop metastability and bolstering overall robustness.

In terms of circuit implementation, the research team employed an adaptive reset technique to ensure precise alignment between the VCO reset voltage and oscillation amplitude. The utilization of a dynamic switched buffer structure and phase folding technology has significantly improved phase extraction efficiency while reducing hardware overhead. Manufactured using a 22nm CMOS process, the chip boasts a compact core area of merely 0.0022 mm² and supports adjustable sampling rates ranging from 500 MS/s to 2.5 GS/s. At a sampling rate of 2 GS/s, the measured Signal-to-Noise and Distortion Ratio (SNDR) reaches an impressive 39.1 dB, and the Walden Figure of Merit (FoM_W) is as low as 31.3 fJ/conv.-step.