During the FPGA prototype verification phase of chip design, designers construct a near-realistic chip prototype on an FPGA for early software debugging and system-level verification. As DDR5/LPDDR5 becomes the mainstream memory standard for high-performance SoCs, mainstream FPGA hardware faces challenges in directly supporting these new memory types due to issues such as incompatible I/O electrical standards and mismatched PHY interface specifications. Replacing the SoC's memory subsystem can lead to distorted performance test results. Therefore, a memory model that is compatible with the designed memory controller and features precise timing is required. By simulating the PHY and memory behavior of DDR5 through a memory model, system functionality, controller logic, and hardware-software collaboration can be thoroughly verified before tape-out, significantly reducing tape-out risks. S2C's DFI adaptation verification solution integrates physical layer functionality, complies with the standard DFI interface protocol, and supports deep debugging through backdoor access, providing a reliable system-level verification environment for high-speed interfaces such as DDR5 and LPDDR5. This solution leverages the existing DDR4 physical interface on the FPGA to simulate the behavior of new memory types like DDR5 and LPDDR5, addressing access challenges in prototype verification and improving debugging efficiency and verification transparency. S2C's memory model supports advanced protocols such as DDR5, enabling users to build a complete, operational, and debuggable prototype verification environment for the memory subsystem. Users can seamlessly integrate it with their proprietary or third-party memory controllers, accelerating end-to-end verification from the controller to the physical interface. The memory test programs passed successfully, with accurate reading and writing of the 32GB space. This case demonstrates that S2C's memory model and backdoor debugging capabilities not only effectively verify the functional correctness of DDR5 controllers but also significantly enhance system integration and debugging efficiency, providing reliable support for prototype verification of complex SoCs.