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On May 14, 2026, TSMC presented its innovative "three-tier cake" theory for AI chips at its technology forum. According to this theory, AI chips can be systematically divided into three distinct layers: the computing layer, the layer encompassing heterogeneous integration and 3D ICs, and the layer dedicated to photonic and optical interconnects. TSMC is currently working on a platform architecture that integrates SoIC, CoWoS, and COUPE optical interconnect technologies. Notably, the COUPE technology boosts bandwidth and energy efficiency, while also minimizing latency through the 3D stacking of electronic and photonic integrated circuits. Mass production of this technology is anticipated within the year, with an ambitious goal to elevate bandwidth density to 4TBps by 2030.
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