On May 14, Tian Boren, Deputy General Manager of Operations and Advanced Technology Engineering at TSMC, announced at the annual technology forum that, propelled by the rapid surge in global AI and high-performance computing (HPC) applications, TSMC is ramping up the expansion of its global wafer fabrication facilities at double the previous rate. Simultaneously, the company is bolstering its advanced process and packaging capabilities. TSMC intends to construct and upgrade 18 semiconductor factories, including five advanced packaging and testing plants. By 2026, TSMC will have built four new wafer fabs and two advanced packaging plants in Taiwan, while continuing to progress its global 12-inch wafer fab network. Regarding overseas expansion, the first wafer fab in Arizona, USA, has initiated mass production of the 4nm process, with an anticipated annual production capacity increase of 1.8 times by 2026. The second wafer fab is set to start mass production of the 3nm process in the latter half of 2027, while the third wafer fab has been completed and will introduce 2nm-class node technology in the future. The first wafer fab in Kumamoto, Japan, has entered mass production for 22nm and 28nm processes, with the second wafer fab expected to begin construction in 2025, producing 3nm technology. The German facility will concentrate on automotive and industrial applications, supporting 28nm, 22nm, 16nm, and 12nm process technologies. In terms of advanced processes, TSMC’s cutting-edge 2nm process has commenced mass production. Following this, based on the 2nm process and integrated with the A16 process, mass production will also proceed as scheduled. To accommodate robust customer demand for the 2nm process, TSMC will concurrently initiate multiple wafer fabs in 2026. The output in the inaugural year of 2nm mass production will be 45% higher than that of the 3nm process during the same timeframe, with 2nm capacity projected to expand at a compound annual growth rate (CAGR) of approximately 70% from 2026 to 2028. Additionally, TSMC will persist in expanding its 3nm and 5nm capacities, with 3nm and 5nm capacities anticipated to grow at a CAGR of around 25% from 2022 to 2027. In the realm of advanced packaging, 3DIC technologies such as CoWoS and SoIC continue to advance, with SoIC-X having already entered mass production. Related capacity is expected to increase by over 80%. To satisfy the intense demand for advanced packaging in AI applications, TSMC will proactively expand its CoWoS and related 3DIC product capacities at a CAGR exceeding 80% from 2022 to 2027.