Samsung Electronics is set to initiate mass production of memory modules adhering to the CXL 3.1 standard in the fourth quarter. In the preceding third quarter, the company had already supplied samples of CMM-D to key server and data center clients, with the scale of production to be finalized following rigorous quality verification. CXL represents a high-speed interconnect standard that builds upon PCIe technology. The CMM-D 3.1 module seamlessly integrates multiple DRAM chips with a dedicated CXL controller, thereby offering reduced latency and enhanced speeds in comparison to its predecessors. CXL technology facilitates memory pooling and serves as a complementary solution to HBM. Previously, Samsung had developed and distributed CMM-D 2.0 samples to a diverse range of customers. Although the company initially aimed to introduce CMM-D 3.1 by the end of 2025, the priority for CXL commercialization has shifted due to the robust demand for general-purpose DRAM and HBM. Market research entities project that the CXL market will expand from $2.1 billion in 2025 to a staggering $16 billion by 2028, thereby bolstering the relevant industrial chain.