Search
Liang Hongzhi and Zhu Zhangming, along with their team from the Key Laboratory of Analog Integrated Circuits at Xidian University, have made remarkable strides in the realm of energy-efficient 8-bit 32GS/s highly digital analog-to-digital converters (ADCs). The team introduced a 16-channel interleaved 32GS/s two-stage sampling architecture voltage-time hybrid domain ADC, which attains a sampling rate of 2GS/s per channel. Operating under the Nyquist input frequency, this ADC achieves an SFDR (Spurious-Free Dynamic Range) of 50.8dB and an SNDR (Signal-to-Noise and Distortion Ratio) of 36dB. Moreover, it maintains stable performance amidst variations in temperature and power supply voltage, rendering it well-suited for ultra-high-speed data processing scenarios.
-
C114 Communication Network -
Communication Home
