The JEDEC Solid State Technology Association has recently disclosed its roadmap for the upcoming iteration of LPDDR6 low-power memory. It is anticipated that individual memory chip capacities will soar to 512GB, significantly surpassing the current mainstream server DDR5, whose individual capacities generally span from 64GB to 128GB. The capacity leap of LPDDR6 is mainly due to the incorporation of a narrower x6 sub-channel mode and the utilization of cutting-edge process technology that enhances the density of individual dies.

In the future, AI servers will be able to effortlessly construct terabyte-scale memory pools. This advancement will minimize data transfer between memory and solid-state drives, and notably double model inference efficiency. Moreover, LPDDR6 operates at speeds surpassing 10.7Gbps, marking a 33% increase over its predecessor, while concurrently reducing power consumption by over 20%. Additionally, the SOCAMM2 compact module standard, which is based on LPDDR6, is currently in development to supersede traditional DDR5 sticks, thereby furnishing AI servers with a memory foundation that boasts higher integration and lower power consumption.