Given the inherent physical limitations, the miniaturization of silicon-based transistors has reached a plateau, posing challenges in meeting the escalating computational needs of avant-garde domains like artificial intelligence. To circumvent this, researchers are channeling their efforts into pioneering novel channel materials and investigating alternatives to the conventional von Neumann architecture, with the aim of maintaining or even surpassing the pace set by Moore's Law. Nevertheless, in systems leveraging binary circuits, the interconnections between and within functional units on a chip continue to present a formidable obstacle. With the escalating density of transistors, the space consumed by these interconnections is projected to outstrip that of logic units, thereby impeding further miniaturization and integration efforts. Multi-valued logic (MVL) emerges as a beacon of hope, offering a viable solution to mitigate this challenge through its superior computational efficiency and enhanced data throughput capabilities.