Recently, the Design Automation Conference (DAC) 2026—a premier international event in the field of Electronic Design Automation (EDA)—has accepted three papers from the National Key Laboratory of Processor Chips at the Institute of Computing Technology, Chinese Academy of Sciences. DAC is renowned for its rigorous selection process, with an acceptance rate of just 23% this year, underscoring the high caliber of the accepted works.

The first paper, titled "Enhancing Fault Tolerance in Large Language Model Inference: A Spatial-Temporal Activation Contextualization Approach," delves into the challenges of fault tolerance during large language model (LLM) inference. It introduces a novel spatial-temporal activation contextualization method that significantly boosts the robustness of LLM inference in resource-constrained settings. This is achieved by optimizing the spatial-temporal characteristics of model activation values, thereby enhancing the model's ability to withstand and recover from faults.

The second paper, "A Unified Hardware Acceleration Architecture for Fully Homomorphic Encryption (FHE): Bridging Compatibility and Performance Gaps," focuses on the burgeoning field of fully homomorphic encryption. It presents a groundbreaking unified hardware acceleration architecture that is compatible with mainstream FHE schemes, such as TFHE. This architecture addresses the long-standing bottlenecks in compatibility and performance of existing FHE accelerators through meticulous algorithm-architecture co-optimization, paving the way for more efficient and secure cryptographic computations.

The selection of these papers by DAC 2026 not only highlights the laboratory's commitment to pushing the boundaries of intelligent and secure computing but also underscores its significant contributions to the global EDA community. These works exemplify the lab's cutting-edge research efforts and its dedication to advancing the frontiers of technology.