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AMD Zen6 Makes First Appearance: Unusual 10-Core Design, 32MB L3 Cache
2 day ago /
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Author：小编
An engineering sample of AMD's Zen6 architecture mobile processor has surfaced in the GeekBench 6 database, codenamed 'Plum-MDS1' (Medusa Point). The processor features a 10-core design, with 1MB of L2 cache per core and a shared 32MB L3 cache. It has a thermal design power (TDP) of 28W and utilizes an FP10 package. The early sample operates at relatively low frequencies, with a base clock of 2.4GHz and actual operation around 1.3GHz. The Zen6 architecture is expected to support various core configurations, potentially reaching up to 24 cores in mobile platforms, and may be manufactured using a 2nm process, with significant improvements anticipated in AI performance.
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