Recently, the team led by Professor Du Yuan and Du Li from Nanjing University made a significant leap forward in the realm of high-speed interconnects for integrated circuits. In collaboration with the research group from T-Head (Shanghai) Semiconductor Co., Ltd., they successfully engineered a 5-channel single-ended 112Gb/s/pin PAM4 transceiver, which incorporates cutting-edge technologies such as 4-aggressor crosstalk cancellation and power supply noise suppression. Though the original title of the achievement was not provided, this remarkable feat was presented at the International Solid-State Circuits Conference (ISSCC) 2026, setting a new world record with an ultra-high edge bandwidth density of 47.0Tb/s/mm. This innovative technology has already been integrated into the development of AI computing chiplets and HBM memory chiplet interfaces, offering crucial technical backing for domestic AI chips to stand toe-to-toe with international advanced counterparts.