Semiconductor giants like TSMC have set up manufacturing facilities in the U.S. as a strategic move to hedge against geopolitical uncertainties. However, these ventures are now grappling with a sharp spike in operating expenses. Based on data from SemiAnalysis, shared by analyst Jukan on platform X, TSMC is poised to see a substantial erosion in its profit margins for chip production in the U.S. market.

Focusing on 5-nanometer process chips, the gross profit margin per wafer at TSMC’s U.S. plant stands at a mere 8%, a stark contrast to the 62% achieved at its Taiwan, China facility—a staggering 54-percentage-point difference. This widening gap is largely attributable to the fact that depreciation costs at the U.S. plant are nearly fourfold those in Taiwan, China. Moreover, labor expenses in the U.S. are considerably higher. When producing wafers using the same process, the U.S. plant’s output may only reach a quarter of that in Taiwan, China, resulting in a dramatic rise in depreciation costs per wafer. Additionally, elevated labor costs and efficiency disparities stemming from cultural differences further inflate operational expenditures.

Former TSMC Chairman Morris Chang once highlighted that the U.S. team’s efficiency in equipment maintenance during breakdowns lags significantly behind that of the Taiwan, China team. Despite these challenges, TSMC remains committed to ramping up its long-term investment in the U.S. supply chain, with plans to allocate up to roughly $300 billion. This investment will span wafer fab networks, advanced packaging, and R&D facilities, in line with the U.S. government’s “America First” economic strategy. Nevertheless, this approach is placing considerable strain on TSMC’s profitability, making the balancing act between geopolitical risk management and economic prudence a pivotal challenge for the company.