In December 2025, Japan's Dai Nippon Printing Co., Ltd. (DNP) made a groundbreaking announcement: the successful creation of a nanoimprint lithography (NIL) mask boasting a circuit linewidth of just 10 nm. This cutting - edge technology is capable of facilitating circuit patterning on a scale equivalent to 1.4 nm - class logic semiconductors.

It's specifically tailored to address the miniaturization demands of state - of - the - art logic chips in various application scenarios. These include smartphones, which are ubiquitous in modern life; data centers, the backbone of digital information storage and processing; and NAND flash memory, a key component in numerous electronic devices.

DNP explained that this innovative technology works by directly imprinting circuit patterns onto substrate materials. This approach offers manufacturers a novel way to cut down on exposure energy consumption and streamline cost structures in certain process steps.

At present, DNP has already kicked off customer evaluations. Looking ahead, the company has set a goal to achieve mass production by 2027. Moreover, it aims to boost the sales of its nanoimprint - related business to a staggering 4 billion yen in the fiscal year 2030.

Regarding the specific processes, DNP has incorporated self - aligned double patterning (SADP) technology. This technology effectively doubles the pattern density, paving the way for nanoimprinting with a 10 nm linewidth.

In addition, DNP will showcase this new NIL nanoimprint lithography mask at SEMICON Japan 2025. The purpose is to foster deeper exchanges and collaborations with global semiconductor manufacturing companies and equipment manufacturers.