In the context of the globalization of integrated circuits and the swift evolution of processor architectures, ensuring privacy and security within chip microarchitectures continues to pose significant challenges in the realm of hardware system design. The broad acceptance of new instruction set architectures, exemplified by RISC-V, has empowered processors to gain notable benefits in terms of energy efficiency and openness. Nevertheless, this shift has also paved the way for new avenues of attack and potential hazards. Traditional side-channel attacks typically exploit high-precision timing instructions to glean information, and processors counter these threats by imposing restrictions on timer access. However, amidst the emergence of novel microarchitecture mechanisms, it remains ambiguous whether these defensive strategies can genuinely eradicate the risks of privacy breaches at the cache level. Hence, it is of paramount importance to undertake proactive research in microarchitecture analysis, reverse engineering, and vulnerability exploration.