On September 4, during the 13th Semiconductor Equipment, Core Components, and Materials Exhibition (CSEAC 2025), Jia Zhaowei, the Vice President of Technology at ACM Research Shanghai, gave a speech. In his speech, he delved into the trends in 3D integration and AI chip technology, the challenges within the electroplating field, as well as the solutions offered by ACM Research.

He highlighted that 3D chip stacking has emerged as the dominant trend. By integrating chips with diverse functions, it enables significantly enhanced performance. This, in turn, imposes more stringent requirements on integrated circuit interconnection technologies and equipment. For instance, the HBM packaging technology has transitioned from using bumps to adopting hybrid bonding for direct interconnection. This shift is propelling the evolution of electroplating technology towards cross-generational applications, such as Through-Silicon Via (TSV) and sub-micron interconnections.

Jia Zhaowei also outlined the key challenges in the electroplating field. These include stress and warping problems arising from chip stacking, the need for coplanarity and uniformity during the shift from round to square wafer processing, and the difficulties in cleaning and electroplating deep holes with high aspect ratios.

Drawing on its extensive technological expertise in the electroplating field, ACM Research has introduced a range of products suitable for multiple scenarios. For example, the front-end damascene electroplating machine employs a dual-anode design, while the electroplating equipment for advanced packaging incorporates a patented second-anode design. At present, ACM Research's electroplating equipment for the integrated circuit sector supports processes down to 28nm and even more advanced nodes. It has achieved large-scale mass production in areas such as TSV, advanced packaging, and third-generation semiconductors.