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Japan's Rapidus has achieved remarkable progress in the development of 2nm process technology. For the first time, the company has publicly disclosed the logic density of its 2HP process node, which stands at an impressive 237.31 million transistors per square millimeter (MTr/mm²). This figure is on par with TSMC's N2 process, which boasts a density of 236.17 MTr/mm². This data underscores Rapidus's ability to compete head-to-head with TSMC in terms of logic density within the 2nm technology realm, showcasing its robust competitive stance. As a pivotal player in Japan's semiconductor industry, Rapidus is ramping up its efforts to develop 2nm process technology and aims to deliver 2nm physical design kits to customers in the first quarter of 2026.
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