Infineon Technologies has fabricated functional silicon carbide (SiC) power semiconductor devices on 300mm wafers at its Villach, Austria, manufacturing site, demonstrating the feasibility of producing wide-bandgap power devices on a larger wafer format. Infineon says the 300mm wafer can accommodate approximately 2.3 times as many chips as a 200mm wafer, opening a potential path toward lower per-device manufacturing costs. The functional devices were fabricated using equipment originally designed for silicon semiconductor production.

The development addresses a persistent constraint in silicon carbide manufacturing: the cost and complexity of growing, slicing and processing high-quality substrates. In parallel with the Villach device demonstration, Infineon has demonstrated the feasibility of its Cold Split wafer-separation technology on 300mm SiC material in Dresden, Germany. Cold Split is designed to reduce material losses relative to conventional wafer sawing. The larger format could increase output per processing cycle, but actual cost improvements will depend on substrate quality, defect density, die yield, utilization and qualification.

The milestone has implications for the emerging 800V DC power architecture in AI data centers. SiC semiconductors can support high-voltage, high-power conversion stages, including solid-state transformers and protection systems that connect utility and facility power to high-voltage DC distribution. Infineon is also developing GaN devices for complementary high-frequency power-conversion applications. The 300mm SiC milestone is a process demonstration, however, not an announcement of qualified high-volume production: Infineon has not provided a 300mm SiC commercial ramp date, manufacturing yield or customer shipment schedule.

Jochen Hanebeck, CEO of Infineon Technologies, said: “This technological milestone further strengthens our leadership in power systems.”

Infineon plans to display a processed 300mm SiC wafer at electronica 2026 in Munich, November 10–13, while continuing its 200mm SiC roadmap.

Key Points

Analysis

Manufacturing economics: The geometric area of a 300mm wafer is 2.25 times that of a 200mm wafer; Infineon cites approximately 2.3 times as many chips per wafer. This does not imply an equivalent reduction in cost per device. The realized economics depend on substrate price, crystalline defect density, wafer breakage, usable die yield, process complexity and equipment utilization. Cold Split could improve substrate utilization by reducing crystal loss during wafer separation, although Infineon has not disclosed cost per qualified 300mm SiC die.

AI data centers and 800V DC: Higher-voltage distribution reduces current for a given power level. A theoretical 1MW load requires 1,250 amperes at 800V DC, compared with roughly 20,833 amperes at 48V, excluding conversion losses. Such systems require appropriate insulation, safe service procedures, switching and fault protection. SiC is relevant to higher-voltage stages such as solid-state transformers; Infineon’s previously announced SiC supply arrangement with Eaton for its medium-voltage solid-state transformer illustrates this application.

Complementary materials: Infineon’s October 27, 2026 announcement of approximately €1.1 billion in 300mm GaN manufacturing investment at Villach targeted production by the end of 2027. GaN and SiC are complementary rather than interchangeable: GaN can support compact, high-frequency conversion closer to loads, while SiC is well established for higher-voltage and higher-power conversion. Infineon has not announced a comparable production start for 300mm SiC.

Next milestones: Repeatable wafer-level yields, device reliability, customer qualifications and a defined production timetable will be necessary to establish commercial readiness. The present announcement demonstrates a manufacturing capability, not volume production economics.

Company Profile: Infineon Technologies