Xsight Labs has expanded its E-Series data processing unit (DPU) portfolio with the E1L, a fully programmable processor delivering up to 200 Gbps of networking throughput within a configurable 25W to 40W thermal design power (TDP). Built on TSMC’s 5nm process and powered by Arm Neoverse N2 cores, the E1L targets edge computing, embedded systems and other power-constrained infrastructure environments. The device extends Xsight Labs’ software-defined DPU architecture beyond its existing 800G E1 platform, allowing operators to deploy networking, storage and security offloads across different performance and power requirements while maintaining a common software environment.

The E1L integrates 8, 16 or 22 Arm Neoverse N2 cores, up to 200 Gbps of networking bandwidth across four SerDes lanes, two DDR5-5200 memory interfaces with inline encryption, and 20 PCIe Gen5 lanes across six dual-mode controllers. Hardware acceleration includes line-rate AES-GCM encryption for IPsec, while software support encompasses standard Linux distributions, XDP, DPDK and SPDK. Xsight Labs offers the E1L as a discrete device, COM Express module and 1RU server. The company specifies three TDP configurations—25W, 30W and 40W—with corresponding typical power consumption of 15W, 18W and 25W.

The E1L shares its architecture and software stack with the company’s 800G E1 DPU, enabling software developed for one platform to operate on the other without proprietary licensing. Xsight Labs expects E1L sampling to begin in the second quarter of 2027 and plans to present the processor at the OCP Global Summit in San Jose, October 12–15, 2026.

Analysis: Extending Programmable DPU Architecture from Hyperscale to Edge

The E1L represents an extension of Xsight Labs’ DPU strategy into lower-power environments while preserving compatibility with the company’s higher-performance E1 processor. The original E1 provides up to 800 Gbps of networking throughput using up to 64 Arm Neoverse N2 cores. Xsight places general-purpose Arm processors directly in the data path and supports programmable networking, storage and security services using standard Linux software frameworks.

The architectural continuity between E1 and E1L gives equipment makers and operators a path to use the same Linux, XDP, DPDK and SPDK software framework across multiple performance tiers. Actual performance portability will depend on workload characteristics, available CPU cores, memory bandwidth and I/O configuration.

Xsight Labs has developed two principal silicon product families: X-Series Ethernet switching processors and E-Series DPUs. The E1L adds a lower-power tier aimed at applications where the full performance and power envelope of an 800G DPU is unnecessary. The next milestone will be silicon sampling in Q2 2027, followed by customer qualification and validation of networking, storage and security workloads within the advertised power envelopes.

We’re tracking developments in networking silicon, programmable DPUs, AI accelerators and next-generation semiconductor architectures at Converge Digest.