Meta's custom AI chip passed six weeks of bug testing without a major architectural problem and is headed to manufacturing in September — a milestone that matters less for what Iris is than for who built it and who else they are building for, according to an internal memo reviewed by Reuters.

Broadcom, the chip design firm working with Meta on Iris, is also the design partner behind Google's seventh-generation Tensor Processing Units and OpenAI's first custom chip, Jalapeño, which went from initial design to a manufacturable blueprint in nine months, as Let's Data Science reported. That makes Broadcom the common thread running through three of the five major custom silicon programs now operating at frontier AI labs — a structural consolidation in AI hardware design that no individual chip announcement quite captures on its own.

The Reuters memo that surfaced the Iris details on July 9 contained an unusual admission. Adopting the latest generation of third-party GPUs at Meta's scale, it read, "has been a heavy lift, and it has cost us time." Iris is the company's formal answer to that problem. It is not a replacement for Nvidia and AMD hardware — the memo makes that explicit. It is a supplement, designed to handle the specific workload that keeps Facebook and Instagram running while Nvidia's chips continue to handle everything else.

Meta Joins a Race That Started Without It

Meta enters custom silicon production later than every other major hyperscaler. Google has shipped seven generations of Tensor Processing Units. Amazon's Trainium 3 reached general availability in December 2025. Microsoft's Maia 200 has been running internally since January 2026, though it has yet to reach general availability for Azure customers and is still reportedly in discussions to land Anthropic as its first major external customer.

OpenAI unveiled Jalapeño, its first custom chip, on June 24, 2026 — less than two weeks before the Iris memo surfaced — in partnership with Broadcom. The table below shows where each major custom silicon program stands as of this writing:

The last column on the right is the one nobody talks about. Every chip in the table, regardless of who designed it, is manufactured by Taiwan Semiconductor Manufacturing Co. — the Taiwanese foundry that produces roughly 90% of the world's most advanced chips. The hyperscaler race to reduce dependence on Nvidia has simultaneously deepened every major AI company's dependence on a single factory-nation.

What Iris Is Built to Do — and Why GPUs Were the Wrong Tool

Iris falls under Meta's MTIA program — Meta Training and Inference Accelerators — a four-generation chip roadmap the company unveiled publicly on March 11, 2026. One earlier chip in the family, MTIA 300, is already running Meta's ranking and recommendation systems in production. Iris is the next step: purpose-built for inference workloads across Facebook, Instagram, and Meta's growing generative AI features.

To understand why that distinction matters, it helps to understand what those workloads actually are. Meta's dominant AI compute task — before and after the generative AI surge — is the deep learning recommendation model (DLRM): the algorithm that decides, in real time, what post, ad, or video appears next in a user's feed. DLRMs are not like the large language models that made GPUs famous. They are memory-bound, not compute-bound. They involve enormous, sparsely accessed embedding tables — sometimes hundreds of gigabytes — that require lookups across irregular data rather than the dense matrix operations GPUs excel at. Running DLRMs on a GPU means leaving most of its raw compute capacity idle while waiting on memory, as Meta's own infrastructure research confirms.

The published research on Meta's second-generation MTIA chip, presented at the International Symposium on Computer Architecture in 2025, quantified that gap: replacing GPUs with the MTIA 2i design cut total cost of ownership by 44% while maintaining competitive performance per watt. The architectural choice that enables that saving is a deliberate departure from GPU convention. Where Nvidia's H100 uses high-bandwidth memory (HBM) — fast and expensive — the MTIA chips use a combination of large on-chip SRAM (fast and local) and cheaper LPDDR5 DRAM. For DLRMs, where the access pattern is sparse and irregular rather than dense and predictable, the SRAM-centric design moves data closer to where computation happens, reducing the expensive memory fetches that slow down GPU-based inference.

The chip is built on an open-source RISC-V instruction set architecture — not a proprietary ISA — and the full software stack runs on PyTorch, vLLM, and Triton, the same tools Meta's AI engineers already use, per the company's March 2026 roadmap post. That was a deliberate decision: past MTIA generations struggled partly because the software environment was unfamiliar. Iris and its siblings are designed to slot into existing workflows without requiring engineers to relearn their tools.

Why Six Months Is the Real Number to Watch

Not all reactions to the Iris announcement were enthusiastic. Daniel Newman, chief executive of the technology research firm Futurum Group, responded to the Reuters report directly: "It isn't replacing AMD and NVDA with in-house. It is augmenting to meet ambitious capacity requirements and demand expectations."

That reading is accurate, and the market reflected it. Nvidia shares fell only modestly when the memo report broke, then recovered the following session — a sign that investors are not pricing in near-term threat to Nvidia's core business, as analysts noted at the time. Deutsche Bank analyst Benjamin Black offered a more specific projection: by combining Iris and Nvidia chips, Meta could reduce data center costs by as much as 35% by 2027, concentrated in inference and recommendation workloads, per his July note.

Meta's own stock reaction on July 9 was complicated. Shares fell initially on the capex implications of the memo, then recovered to close up approximately 4.7% — but primarily on a separate announcement about developer access to a new AI coding model, not the chip news, as market coverage confirmed. Bank of America has been explicit that Iris is not responsible for 2026 cost savings, which instead come from Meta's data center construction and procurement discipline. Iris is a 2027-and-beyond story.

What makes the Iris timeline unusual is not the September production date but the cadence that follows it. Meta is targeting a new MTIA generation approximately every six months through 2027, per its official roadmap. A standard GPU product cycle runs 18 to 24 months. The faster pace is made possible by the same modular, reusable chiplet approach that lets each generation share chassis and rack infrastructure with the last — meaning a new chip generation does not require a new data center buildout to deploy.

Wall Street's patience with Meta's spending trajectory is not unlimited. In April, Meta's first-quarter 2026 capital expenditure surge prompted JPMorgan to downgrade the stock, and shares lost roughly 10% across two trading sessions on investor concern that returns were not keeping pace with spending, as TipRanks reported. Iris does not resolve that concern. It adds another line item to a budget analysts are already scrutinizing closely.

A Complicated History Behind a Clean Test

The six weeks of clean testing are meaningful specifically because Meta's in-house chip program has not earned the benefit of the doubt. Reuters described the MTIA effort as one that "has floundered since its launch more than half a decade ago," in the same memo report. The Information reported in February 2026 that Meta had scrapped a more ambitious training chip, code-named Olympus, after its supporting software proved less stable than Nvidia's ecosystem and its cutting-edge 2-nanometer design raised manufacturing risk, as Dataconomy reported citing The Information. Olympus was originally designed to substitute for Nvidia hardware in Meta's training clusters entirely. Instead, Meta signed a multiyear deal worth several billion dollars to lease Google's TPUs while simultaneously expanding its Nvidia purchases under a separate multiyear agreement.

The distinction that chip analysts drew after the Olympus cancellation turned out to be exactly the one Meta has since internalized: training workloads evolve constantly as new model architectures emerge, making a fixed-function training ASIC a high-risk design bet. Inference workloads — especially for recommendation and ranking — are far more stable. Meta's DLRM-serving workload has been running at scale for years; the algorithm's inputs change daily but its computational pattern does not. That stability is what makes a purpose-built inference chip a defensible investment rather than a stranded asset.

The scale of the investment being hedged helps explain the urgency. Meta projects capital expenditure of up to $145 billion on AI infrastructure in 2026 alone — one of the largest single-year infrastructure spends in corporate history, per reporting on the Reuters memo. The company added one gigawatt of computing capacity in the first half of the year and plans to add roughly 5.5 more before year-end, reaching a total of approximately seven gigawatts. The 2027 target is 14 gigawatts — enough to power more than 11 million homes, as Let's Data Science noted.

To secure the components for that buildout, Meta has locked in long-term supply agreements with Samsung Electronics for memory chips, SanDisk for flash storage, and Sumitomo Electric for fiber-optic equipment — moves designed to guarantee access before industry-wide demand pressure makes procurement harder, per the Reuters memo. Morgan Stanley analysts coined a term for that pressure: "chipflation" — the semiconductor price inflation that has made AI infrastructure costs a broader macroeconomic concern, as Reuters reported from the bank's June 3 note.

Broadcom's Consolidation Is the Bigger Story

The single most consequential finding buried inside the Iris announcement is not about Iris at all. It is about Broadcom.

Three of the five major custom AI chip programs currently running at frontier labs — Meta's Iris, Google's TPU, and OpenAI's Jalapeño — route through the same design firm. Amazon and Microsoft work with Marvell, not Broadcom, on Trainium and Maia respectively. Together, Broadcom and Marvell control roughly 95% of the custom AI ASIC co-design market.

For Broadcom, this consolidation has produced a revenue trajectory that has outpaced nearly every forecast. The company reported $10.8 billion in AI semiconductor revenue in its fiscal second quarter of 2026, a 143% increase year over year, per its official earnings release. CEO Hock Tan guided to $16 billion in the third quarter and projected AI chip revenue in excess of $100 billion for fiscal 2027, in the same earnings call.

That growth is directly tied to the same dynamics making Iris possible. Custom AI chips make economic sense only at hyperscaler scale — when a company is running billions of the same type of inference query per day, the fixed cost of designing purpose-built silicon gets amortized across enough queries to justify the investment. For a company running recommendation models that generate trillions of predictions daily, every percentage point of efficiency gained on a custom chip translates into enormous cost savings at volume. Broadcom's position as the preferred design partner captures a large share of that economics on the other side.

The Concentration Risk Nobody Is Talking About

There is a structural irony in the hyperscaler custom silicon race that the Iris announcement makes visible. Meta, Google, and OpenAI are each building custom chips explicitly to reduce their dependence on a single supplier — Nvidia. In doing so, all five major programs have concentrated their fabrication needs at a single location: TSMC's factories in Taiwan.

TSMC produces roughly 90% of the world's most advanced semiconductors. TSMC has built factories in Arizona, Japan, and Europe, but those facilities do not produce chips at the leading-edge nodes used for AI accelerators — and even chips made in Arizona are typically sent back to Taiwan for advanced packaging, because the packaging infrastructure required for AI accelerators does not yet exist at scale outside Taiwan.

The practical implication is concrete: a disruption to TSMC's Taiwan operations — from military conflict, a blockade, a major natural disaster, or a regulatory action — would halt all five hyperscaler custom chip programs simultaneously. The Iris announcement adds Meta to that list. The hyperscalers are trading Nvidia dependence for TSMC dependence. One is a domestic supplier with competitors. The other is a near-monopoly anchored to an island approximately 100 miles wide, as analysts tracking the semiconductor supply chain have documented.

This does not mean custom silicon is a mistake. It means the risk that custom silicon was designed to address — vendor lock-in — has been redirected rather than eliminated. That distinction matters more as AI infrastructure becomes the operational backbone of every major technology company's business.

September Is the First Real Test

Iris's September production date gives investors, analysts, and competitors a concrete milestone to watch. Six clean weeks of testing in a controlled environment is one thing. Delivering real inference workloads at production scale across Meta's global data center footprint is another.

The chip landscape it enters is more crowded than when the MTIA program began. Microsoft's Maia 200 has run internally for months but has not reached general availability for Azure customers. Amazon's Trainium 3 is shipping but competes in a market where Nvidia's H100 and H200 remain the default for most enterprise AI workloads. OpenAI's Jalapeño was unveiled in June and is still months from deployment.

What Meta has in common with all of them — and what the Broadcom table makes plain — is that in-house silicon is no longer a competitive differentiator so much as a strategic cost hedge. The hyperscalers are not trying to out-Nvidia Nvidia. They are trying to reduce the fraction of their AI infrastructure budget that flows to third parties for workloads they understand better than anyone.

For Meta, whose advertising-driven business model depends on recommendation and ranking systems running billions of inferences per day, Iris is a bet that its specific workloads are stable enough, and large enough in volume, to justify the cost and complexity of building from scratch. Its chip designers built the same bet for Google and OpenAI at the same time. September is when Meta finds out if the bet holds at real scale.

Frequently Asked Questions

Will Meta's Iris chip replace Nvidia GPUs?

No. The internal Meta memo that revealed Iris explicitly frames the chip as a supplement to, not a replacement for, the large volumes of Nvidia and AMD GPUs Meta continues to purchase. Iris is designed for a specific category of workload — ranking and recommendation inference — where custom silicon outperforms GPUs on cost efficiency. Nvidia hardware remains Meta's primary tool for large-scale AI training and for inference workloads that require flexibility across different model architectures.

Why does Meta's chip use RISC-V architecture instead of a GPU-based design?

Meta's dominant AI workload — the deep learning recommendation model that determines what appears in Facebook and Instagram feeds — is memory-bound rather than compute-bound. It involves enormous, sparsely accessed data tables that require irregular memory lookups, not the dense matrix operations that GPUs are optimized for. A GPU running these models leaves most of its raw compute capacity idle while waiting on memory. The MTIA chip uses a RISC-V instruction set, large on-chip SRAM, and cheaper LPDDR5 memory instead of GPU-standard high-bandwidth memory — an architecture that matches the actual data access patterns of Meta's workload. Published research on the second-generation MTIA design found this approach cut total cost of ownership by 44% versus GPUs for the same inference tasks.

If every hyperscaler is building custom AI chips to reduce Nvidia dependence, why are all their chips made by the same company?

Because there is effectively only one company capable of fabricating leading-edge AI chips at scale: TSMC. All five major hyperscaler custom chip programs — Meta, Google, Amazon, Microsoft, and OpenAI — are manufactured by TSMC in Taiwan. TSMC controls roughly 90% of the world's most advanced chip production, and its leading-edge fabrication remains concentrated in Taiwan. TSMC has opened factories in Arizona, Japan, and Europe, but those do not yet produce the leading-edge nodes used for AI accelerators. The hyperscaler push to diversify away from Nvidia has concentrated the industry's fabrication dependency more deeply in a single geographic location — a systemic risk that the Iris announcement, like every other custom chip announcement before it, does not address.

How does Broadcom benefit from designing chips for Meta, Google, and OpenAI simultaneously?

Broadcom is the preferred custom AI chip design partner for three of the five major hyperscaler programs, and its AI semiconductor revenue reflects it: $10.8 billion in the fiscal second quarter of 2026, up 143% from the same quarter a year earlier. Broadcom's CEO has projected AI chip revenue in excess of $100 billion for fiscal 2027. The company's position is structurally advantaged: it does not need to choose a winner in the race between Meta, Google, and OpenAI, because it is the shared design partner whose business grows regardless of which company's chip performs best. Together with Marvell — which handles Amazon and Microsoft — Broadcom controls roughly 95% of the custom AI ASIC design market.