On June 8th, Cadence joined forces with NVIDIA to unveil the industry's pioneering fully autonomous AI-driven virtual engineer tailored specifically for chip design. This breakthrough elevates the Chip Stack AI super agent to a Level-5 autonomous status. Seamlessly integrating Cadence's EDA (Electronic Design Automation) tools with NVIDIA's sophisticated Nemotron large model, and utilizing the secure NVIDIA Open Shell sandbox environment, this solution ensures robust protection for data and intellectual property.

The AI virtual engineer is engineered to autonomously navigate and complete the entire chip design workflow, encompassing even the most intricate verification tasks. Notably, when this agent collaborates with Cadence Xcelium Logic Simulation and Jasper Formal Verification tools for simulation operations, it dramatically shortens the RTL (Register Transfer Level) verification cycle. This process, which traditionally spanned around five weeks, is now accomplished within a single day, marking an efficiency enhancement exceeding 40-fold.