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Arm unveiled the Neoverse CSS N4 — codenamed 'Ranger' — the next generation of its semi-custom server platform, doubling the per-die core ceiling to 128, adding LPDDR6 memory support for the first time in an N-series compute subsystem, and advancing I/O connectivity to PCIe Gen 7. The platform is not a finished processor: it is a pre-validated design framework that chip makers configure for their own requirements — the same model that produced Microsoft's Azure Cobalt 100, AWS's Graviton family, and the data processing units at Nvidia and Intel. The announcement, made at Arm's annual Arm Everywhere China conference in Shanghai, positions the efficiency-focused N-series on a separate architectural path from the V-series chips already covering TechTimes' Arm beat — making CSS N4's deployment targets, design tradeoffs, and new I/O capabilities the part of Arm's data center story that has not yet been told.

CSS N4 Belongs to the Part of Arm That Is Not the AGI CPU

To understand CSS N4's significance, it helps to distinguish the two tracks Arm's data center story now runs on simultaneously.

The V-series track — Neoverse V3 cores — is the high-performance path. It powers the Arm AGI CPU, AWS's Graviton5 192-core server chip, Google's Axion processor, and Microsoft's Cobalt 200. These are chips designed to maximize raw throughput and single-thread performance. They are the headline chips of the Arm server story.

The N-series track — Neoverse N-class cores — is the efficiency path. Its design philosophy prioritizes performance-per-watt over peak throughput. Microsoft's original Azure Cobalt 100 was built on N-series (Neoverse N2) cores. Intel's IPU Adapter E2100 — a data processing unit, not a general-purpose CPU — runs on Neoverse N1 cores. These chips serve scale-out cloud workloads, networking accelerators, data processing units, and smart network interface cards, where the operating constraint is power efficiency at high core counts rather than peak computational intensity.

CSS N4 is the N-series platform's step up to the 3nm era. Its 128-core ceiling matches the V-series ceiling, but the cores themselves — internally codenamed Dionysus — are tuned for the N-series mission: more efficient parallel compute across a larger number of simultaneous light-to-medium workloads, rather than the highest possible single-core speed. The new capabilities announced — LPDDR6, PCIe Gen 7, native FP8 and MMLA hardware acceleration — are specifically chosen to advance the efficiency track's ability to serve the next generation of AI infrastructure, not to match the V-series at its own game.

What CSS N4 Actually Includes

Arm's Compute Subsystem program delivers a pre-validated bundle of CPU cores, coherent mesh network interconnect, memory controllers, and I/O fabric — configurable by the customer but pre-integrated and tested as a system. That pre-integration is the product's value: it reduces the engineering and risk cost of building a custom server chip by allowing partners to start from a proven foundation rather than assembling individual IP blocks from scratch.

CSS N4 configurations range from 8 to 128 Neoverse N4 cores per die, clocked at up to 3.8 GHz — Arm's widest core-count range in any CSS to date. Each core carries 2 MB of private L2 cache, plus 64 KB of L1 instruction cache and 64 KB of L1 data cache. At the die level, the platform provides up to 256 MB of shared L3 cache — four times the 64 MB ceiling of the CSS N2 generation.

For memory, CSS N4 is the first N-series compute subsystem to support LPDDR6 (the JEDEC JESD209-6 standard ratified in July 2025), alongside DDR5 and MRDIMM. LPDDR6 runs at 8,000–12,000 MT/s in CSS N4's supported configuration, covering the lower-to-mid range of the standard's 10,667–14,400 MT/s ceiling. The standard delivers approximately 28.5 to 38.4 GB/s per device at those rates. The practical advantage over DDR5 is bandwidth efficiency per watt — important for power-constrained networking and edge-cloud deployments where bandwidth-to-power ratio, not absolute capacity, governs the design.

For I/O, CSS N4 supports up to 128 lanes of PCIe 7.0 or 6.0 — doubling the 64-lane PCIe 5.0 ceiling of CSS N2. PCIe Gen 7, finalized by PCI-SIG in mid-2025, runs at 128 GT/s per lane, delivering up to 512 GB/s bidirectional bandwidth in a x16 configuration. At 128 lanes, an N4-based chip can support eight x16 PCIe Gen 7 accelerator connections — enough bandwidth to host a dense cluster of AI accelerators from a single data processing unit or host CPU die. CXL 4.0 is supported alongside PCIe, enabling future N4-based chips to participate in coherent disaggregated memory architectures.

Multi-die scalability is built in. CSS N4 supports multi-chiplet and multi-socket configurations via UCIe (Universal Chiplet Interconnect Express) chip-to-chip links, as well as partner-specific physical layer interfaces, allowing designs to scale well past the 128-core per-die ceiling.

How CSS N4 Compares to Its Predecessor

The contrast with CSS N2 is the clearest way to quantify CSS N4's generational advance. CSS N2 topped out at 64 cores per die, 1 MB of L2 cache per core, 64 MB of shared L3 cache, and 64 lanes of PCIe 5.0. Memory support was DDR5 or LPDDR5.

CSS N4 doubles the core ceiling to 128, doubles L2 per core to 2 MB, quadruples L3 to 256 MB, doubles PCIe lane count to 128 and advances the interface by two generations to Gen 7, and introduces LPDDR6 as a new memory option. Arm's internal performance estimate — using a reference configuration of 128 cores at 3 GHz with 2 MB L2 — claims twice the socket-level performance versus the Neoverse CSS N3, 1.75 times the memory bandwidth, and 1.25 times the performance-per-watt. Those figures are Arm's own measurements, not independent benchmarks, and no partner silicon based on CSS N4 has been announced — meaning real-world validation awaits production chips.

What CSS N4 Is for in an Agentic AI Rack

The platform's announced workload targets — cloud scale-out, networking, and agentic AI infrastructure — align with a specific structural shift underway in data center design.

Agentic AI workloads, in which AI agents plan and execute multi-step tasks rather than responding to single queries, impose a fundamentally different demand on compute infrastructure. Where conventional large language model inference concentrates work on GPUs, agentic workflows require continuous CPU-side orchestration between each GPU inference call: scheduling sub-agents, routing tool calls, managing state, and handling the data movement that keeps accelerators fed. Analysis from TrendForce in 2026 found that the CPU-to-GPU ratio in agentic AI deployments is expected to shift from the traditional 1:4 to 1:8 range toward approximately 1:1 — a structural increase in CPU core demand that requires a different kind of server chip from the high-performance V-series designs covering raw inference.

N-series chips are suited to this orchestration layer precisely because they optimize for parallel efficiency at high core counts rather than single-thread peak performance. An N4-based chip with 128 cores, LPDDR6 bandwidth, and 128 PCIe Gen 7 lanes is positioned as a DPU or scale-out orchestrator — the chip type that sits alongside a GPU cluster and manages the workload distribution, data routing, and inter-agent communication that an agentic AI system requires. This is not the same job as the Arm AGI CPU (which is a full host-CPU competitor to Intel and AMD) or Graviton5 (which is a general-purpose cloud CPU for arbitrary workloads). CSS N4 targets the networked, power-efficient middle of the rack.

Samsung Foundry and Export Control Context

The original draft noted only TSMC's N3P process. The full picture is broader: Arm has also designated Samsung Electronics' SF2 (first-generation 2nm) and SF2P (second-generation 2nm) foundry processes as supported nodes for CSS N4 designs. This dual-foundry approach, covering both TSMC and Samsung, gives CSS N4 customers access to two of the world's most advanced process nodes simultaneously — a supply chain optionality that purely TSMC-dependent designs do not have.

One early adopter has been confirmed. Hongjun Microelectronics, a Chinese chip design company, is among the first partners adopting CSS N4 for custom server chip designs, announced at the Arm Everywhere China conference. The involvement of a Chinese foundry customer is notable in light of the export control history Arm has navigated: in 2022, the UK and US governments revoked export licenses for Arm's Neoverse V-series designs to Alibaba, citing concerns about military end-use. The Neoverse N-series — the efficiency track, not the maximum-performance V-series — has historically sat below the export control threshold that triggered that restriction. Chip designers evaluating CSS N4 in export-sensitive markets should confirm applicable licensing conditions with Arm directly, as that landscape evolves with each generation.

AGI CPU Simultaneous Update: Oracle and ByteDance Join

Alongside CSS N4, Arm used the Arm Everywhere China event to confirm two additional customers for its AGI CPU — the 136-core, Neoverse V3-based server processor Arm launched in March 2026, its first in-house chip in 35 years. Oracle and ByteDance's cloud division, Volcano Engine, joined a roster that already includes Meta, OpenAI, Cloudflare, SAP, Lenovo, and others.

The AGI CPU and CSS N4 are designed to coexist rather than compete for the same customer. The AGI CPU is a finished production chip — a turnkey solution for organizations that want to deploy Arm-based data center CPUs without building their own silicon. CSS N4 is a design platform for organizations with the engineering capability to build custom chips and the specific requirements that make customization worth the investment. Together they represent Arm's two answers to the same underlying shift: the data center is moving to Arm, and different organizations will get there by different routes.

What Comes Next

No silicon partners for CSS N4 have been announced beyond Hongjun Microelectronics. Partner product timelines are consistent with how the CSS model has always worked: a small number of large contracts is sufficient for commercial significance, and partner announcements typically follow after design engagement begins. Graviton5 (Neoverse V3-based, 192 cores) launched in June 2026 with four chiplets and a single-socket design — a route available to CSS V4 customers in due course.

The companion V-series platform, CSS V4 (codenamed Vega), is also in development according to Arm's roadmap and is expected to enter production alongside CSS N4 partners. CSS N4-based products arriving at market — likely over the next one to two years — will be the first server chips to carry LPDDR6 and PCIe Gen 7 connectivity in an Arm efficiency-optimized design, and will compete against whatever x86-based DPU and networking platforms Intel and AMD field on the same timeline.

For cloud operators and data center architects, CSS N4 is the blueprint for the next tier of specialized silicon in a heterogeneous AI rack. For Arm, it extends the CSS program's track record — which already includes the Cobalt 100 and multiple DPU designs — into the 3nm era with a specification sheet that closes the I/O gap with the most advanced server interconnects available.

Frequently Asked Questions

What is the Arm Neoverse CSS N4 'Ranger' platform, and how is it different from the Arm AGI CPU?

CSS N4 is a semi-custom design framework that chip makers configure for their own requirements — setting core count, cache size, memory type, and I/O lanes — within a pre-validated Arm-provided foundation. The AGI CPU is a finished, production-ready processor that Arm sells directly. CSS N4 uses Neoverse N4 cores (codenamed Dionysus) optimized for performance-per-watt and scale-out efficiency; the AGI CPU uses Neoverse V3 cores optimized for maximum throughput. A cloud provider building a custom networking chip would use CSS N4; a company that wants a ready-made Arm server CPU without building its own silicon would use the AGI CPU.

Why does CSS N4 support LPDDR6 and PCIe Gen 7, and what does that mean for server chips?

LPDDR6 (the JEDEC JESD209-6 standard, ratified July 2025) delivers approximately 28.5 to 38.4 GB/s of bandwidth per device at data rates of 10,667 to 14,400 MT/s, with lower power consumption than DDR5 at equivalent speeds — making it attractive for networking chips and DPUs where bandwidth-per-watt, not maximum DRAM capacity, governs the design. PCIe Gen 7 runs at 128 GT/s per lane, delivering up to 512 GB/s bidirectional in an x16 configuration. CSS N4's 128 PCIe Gen 7 lanes — doubled from CSS N2's 64 PCIe Gen 5 lanes — means an N4-based chip can support eight x16 Gen 7 accelerator connections, dramatically increasing the accelerator attachment density a single chip can manage.

When will server chips based on CSS N4 be available, and who will build them?

No silicon partners beyond Hongjun Microelectronics (a Chinese chip design company announced at Arm Everywhere China) have been confirmed. CSS N4 is a design platform, not a finished chip, so availability depends on when partners complete their chip designs and bring products to market — typically a one-to-two-year timeline from platform announcement to production silicon. The CSS model has historically required only a small number of large contracts to be commercially significant; partner announcements are expected to follow.

What is the connection between CSS N4 and agentic AI?

Agentic AI systems run many concurrent agent loops — each requiring CPU-side orchestration between GPU inference calls to schedule sub-agents, route tool calls, and manage state. TrendForce's 2026 analysis found the CPU-to-GPU ratio in agentic deployments shifting from the traditional 1:4 to 1:8 range toward approximately 1:1, creating structural demand for high-core-count, power-efficient server chips. CSS N4's profile — 128 cores optimized for parallel efficiency, LPDDR6 bandwidth, and dense PCIe Gen 7 I/O — is aligned with the DPU and scale-out orchestration tier that agentic AI infrastructure requires alongside GPU clusters.