VeriSilicon disclosed that as of the end of September 2026, its order backlog reached 18.569 billion yuan, up 265.90% from the end of last year and 49.16% from the end of the second quarter, remaining at a high level for 12 consecutive quarters. Design service orders typically require a 9-to-12-month design and development cycle before they are gradually converted into revenue, while mass production service orders usually take 6 to 18 months from signing to completion of production and delivery. The company expects to achieve positive adjusted EBITDA in the second half of 2026 and to achieve positive full-year adjusted net profit attributable to shareholders in 2027.