IBM Develops Dual-Architecture Mainframe Chip with Single Core Capable of Parallel Native Execution of Arm and Z Instruction Sets
4 hour ago / Read about 0 minute
Author:小编   

IBM unveiled its next-generation mainframe processor at the Hot Chips 2026 conference. This processor features a dual-architecture design, with cores capable of natively executing both IBM's proprietary instruction set and the Arm instruction set, enabling nanosecond-level switching. Based on a 2-nanometer process, the processor integrates 11 high-performance cores with clock speeds exceeding 5.7GHz, along with an AI inference accelerator, an on-chip DPU, and a large-capacity cache. It supports simultaneous operation of the Arm-native Linux software ecosystem and z/OS transaction processing workloads on the same chip, without the need for emulation or additional standalone Arm cores. This design aims to help enterprises more easily introduce Linux-based cloud-native applications and AI workloads while retaining critical transaction processing operations, thereby supporting the mainframe's key role in the AI era.

  • C114 Communication Network
  • Communication Home
7 X 24 Track global technological trends
Hot Topic