SK Hynix is introducing advanced packaging technologies such as Intel EMIB for its next-generation high-bandwidth memory (HBM), with plans to eventually achieve 3D packaging. At the 2026 Hot Chips conference, Jaesik Lee, Vice President of Packaging Engineering at SK Hynix, delivered a presentation titled 'Advanced Packaging for High-Bandwidth Memory,' detailing how the company is leveraging advanced packaging technologies to drive the development of HBM products. Current HBM achieves 3D stacking through through-silicon vias (TSVs), reaching up to 16 layers. Compared to traditional GDDR6, HBM3E offers up to 144GB capacity and 4TB/s bandwidth while saving space. SK Hynix's HBM4 will feature 24Gb DRAM density and a total capacity of 36GB, with an IO speed of 8Gbps, bandwidth exceeding 2TB/s, and power consumption reduced by over 40%. To address challenges posed by surging bandwidth demands, SK Hynix is exploring future methods such as hybrid bonding to break through the 16-layer stacking limit. Additionally, the company plans to tackle power consumption issues by increasing the number of TSVs, improving IO speed through logic process integration, and optimizing the power distribution network. Notably, SK Hynix mentioned Intel EMIB packaging technology in its 2.5D HBM solution and is rumored to be collaborating with Intel in the memory sector. Looking ahead, SK Hynix is focusing on 3D integration technology, aiming to stack HBM directly on top of accelerators.