On August 5, reports indicated that on August 4 (Eastern Daylight Time), Samsung Electronics unveiled its prototype of V10 Bonding V-NAND (BV-NAND) at the Future of Memory and Storage Summit (FMS) held in Santa Clara, California. This chip employs a structure boasting over 400 layers and incorporates a novel wafer bonding architecture, thereby enhancing both storage density and performance. Samsung asserts that the BV-NAND technology enhances storage density by approximately 58% compared to its predecessor, the V9 NAND. Moreover, it elevates read, write, and input/output performance to cater to the escalating demands of AI systems for storage solutions that are both high-capacity and energy-efficient.

Furthermore, Samsung showcased the industry's pioneering zHBM and zNAND-O architecture concept models. These models facilitate the storage of more data within a compact footprint by vertically stacking memory cells. In contrast to traditional packaging methods, where HBM and AI processors are positioned side by side, Samsung's zHBM adopts a vertical stacking approach for memory atop AI accelerators. This design reduces data transmission distances, thereby enhancing bandwidth and energy efficiency. Samsung has stated that its wafer bonding technology is anticipated to achieve a storage density exceeding ten times that of traditional HBM5 memory. Additionally, it is expected to triple energy efficiency and reduce thermal resistance by more than half.