Recently, the EDA Center at the Institute of Microelectronics has been concentrating on the demands of device-circuit co-design in the post-Moore era. This focus includes delving into critical areas such as interface quantum transport, logical unit interconnection, and non-Fourier heat transfer modeling. Significant strides have been made in the realm of TCAD simulation for 2D memories and cutting-edge logic devices. Specifically, for 2D material flash memories, the institute, in partnership with Fudan University, has developed a time-dependent quantum transport simulation framework. This framework elucidates the sub-nanosecond programming mechanisms and lays a solid foundation for optimizing interfaces and barriers. In the case of CFET devices, the research team has introduced an innovative hybrid channel interconnection integration architecture scheme, along with a collaborative optimization process. This approach effectively reduces both routing and cell area. Moreover, to address the self-heating challenges stemming from device scaling and 3D stacking, the team has established a non-Fourier transient thermal model. They have also proposed a method to mitigate hotspot temperatures by adjusting metal connection structures. The pertinent findings have been published in esteemed journals such as IEEE Electron Device Letters and IEEE Transactions on Electron Devices.