Sun Depeng and Bu Feng, along with their research team from the Key Laboratory of Analog Integrated Circuits at Xidian University, have achieved a notable milestone in the development of ultra-low-jitter phase-locked loop (PLL) chips. Leveraging a 65nm CMOS process, the team successfully designed a 13GHz PLL chip that significantly minimizes jitter—a critical challenge in traditional charge-pump PLLs due to noise and unwanted spurious signals (spurs). The innovation lies in the chip’s architecture: it integrates a frequency-phase detector enhanced by a resistive time amplifier and a highly stable series-resonant voltage-controlled oscillator (VCO), enabling exceptional jitter performance. Furthermore, the incorporation of a sampling filter and an optimized loop design effectively suppresses reference spurs, enhancing overall signal purity. This breakthrough technology holds broad applications in high-speed wired SerDes interfaces, direct RF sampling data conversion systems, and radar systems, where low-jitter timing is essential for reliability and performance. The research findings were published in the IEEE Journal of Solid-State Circuits in 2026, marking a significant contribution to the field of integrated circuits.