Zhao Xiaoteng and Zhu Zhangming's team, hailing from the Key Laboratory of Analog Integrated Circuits at Xidian University, has achieved notable advancements in the realm of energy-efficient high-speed data interface chips. Leveraging a 65nm CMOS process, the team has successfully developed a 9–21 Gb/s frequency-multiplying subsampling (FXSS) clock and data recovery (CDR) circuit. This circuit stands out for its exceptional energy efficiency and compact size, effectively mitigating both in-band and out-of-band noise. It employs an inductor-less architecture and integrates an embedded 1:3 demultiplexer. These features substantially cut down on the area and power consumption typically associated with clock recovery, data retiming, and on-chip clock distribution in high-speed serial interfaces. As a result, it is well-suited for applications such as multi-channel SerDes interfaces in data centers and ultra-short-reach chiplet interconnections. The pertinent research findings have been published in the IEEE Journal of Solid-State Circuits.