Samsung Electronics has made a significant leap forward in DRAM manufacturing technology, successfully creating operational wafers at the sub-10 nanometer scale. This achievement represents a pivotal step in surmounting the notorious '10-nanometer hurdle.' Last month, Samsung leveraged a 4F² cell architecture and the Vertical Channel Transistor (VCT) methodology to fabricate wafers through the 10a process, verifying their efficacy. The company aims to finalize the development of 10a DRAM utilizing this architecture within this year and commence large-scale production by 2028. Moreover, Samsung intends to persist with the 4F² and VCT configurations throughout the 10a, 10b, and 10c phases, transitioning to 3D DRAM technology beginning with the 10d phase. The crux of this technological triumph lies in the incorporation of two novel technologies and alterations to core materials. Industry experts anticipate that Samsung's successful production of these wafers will expedite the progression and mass production of DRAM. Meanwhile, other manufacturers have pursued distinct strategies: Micron is sticking to its current design, Chinese manufacturers are vigorously advancing 3D DRAM development, and SK Hynix plans to implement relevant technologies at the 10b node.