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According to reports, Samsung Electronics has made a significant breakthrough in DRAM manufacturing technology, successfully producing working wafers at the sub-10nm level for the first time. Utilizing 4F² architecture and Vertical Channel Transistor (VCT) technology, the actual circuit line width is approximately 9.5 to 9.7 nanometers. This achievement was first presented as a 16Gb DRAM prototype at the ISSCC 2026 conference in February this year, marking a new path for shrinking DRAM memory cell sizes to their physical limits. Samsung plans to complete the development of 10a DRAM in 2026, conduct quality testing in 2027, and commence mass production in 2028. By reducing cell area by 30% to 50%, this technology enhances capacity and speed while lowering power consumption, laying the foundation for future DRAM development.
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