Recently, Long Xiang, a master's student from the Chip and Security Laboratory (CSL) at Hangzhou Dianzi University, working under the expert guidance of his supervisor, Professor Xia Yingjie, joined forces with research teams from Central South University and Huazhong University of Science and Technology. Together, they accomplished a research project titled "VerilogLAVD: LLM-Aided Pattern Generation for Verilog CWE Detection". This research has been approved for presentation at the main conference of the 64th Annual Meeting of the Association for Computational Linguistics (ACL '26), a conference categorized as CCF-A, which signifies its high academic standing.

The research focuses on the challenge of detecting security vulnerabilities in Verilog code, a critical issue in chip design. It introduces a method for generating graph traversal rules, with the assistance of large language models (LLMs). This innovative approach involves constructing a Verilog Property Graph (VeriPG) that incorporates both syntactic and semantic information from the code. By doing so, it significantly boosts the consistency and accuracy of vulnerability detection processes.

Experimental results have shown that, when compared to existing baseline models, this method achieves substantial improvements in F1 scores across the detection of various common security vulnerability types. This advancement represents a meaningful step forward in enhancing the security and reliability of chip designs through more effective vulnerability detection techniques.